Datasheet

Gigabit LAN Configuration Registers
238 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
6.2.4 GBECSR_2C—Gigabit Ethernet Capabilities and Status
Register 2C
Address Offset: MBARA + 2Ch Attribute: R/W
Default Value: 00000000h Size: 32 bits
6.2.5 GBECSR_F00—Gigabit Ethernet Capabilities and Status
Register F00
Address Offset: MBARA + F00h Attribute: R/W/V
Default Value: 00010008h Size: 32 bits
6.2.6 GBECSR_F10—Gigabit Ethernet Capabilities and Status
Register F10
Address Offset: MBARA + F10h Attribute: R/W/SN
Default Value: 0004000Ch Size: 32 bits
Bit Description
31 WOL Indication Valid (WIV) — R/W.
Set to 1 by BIOS to indicate that the WOL indication setting in bit 30 of this register is valid.
30 WOL Enable Setting by BIOS (WESB) — R/W.
1 = WOL Enabled in BIOS.
0 = WOL Disabled in BIOS.
29:0 Reserved
Bit Description
31:6 Reserved
5 SW Semaphore FLAG (SWFLAG) — R/W/V.
This bit is set by the device driver to gain access permission to shared CSR registers with the
firmware and hardware.
4:0 Reserved
Bit Description
31:7 Reserved
6 Global GbE Disable (GGD)— R/W/SN.
Prevents the PHY from auto-negotiating 1000Mb/s link in all power states.
5:4 Reserved
3 GbE Disable at non D0a — R/W/SN.
Prevents the PHY from auto-negotiating 1000Mb/s link in all power states except D0a. This bit must
be set since GbE is not supported in Sx states.
2 LPLU in non D0a (LPLUND) — R/W/SN.
Enables the PHY to negotiate for the slowest possible link in all power states except D0a.
1 LPLU in D0a (LPLUD) — R/W/SN.
Enables the PHY to negotiate for the slowest possible link in all power states. This bit overrides bit 2.
0 Reserved