Datasheet

Gigabit LAN Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 237
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
6.2.1 GBECSR_00—Gigabit Ethernet Capabilities and Status
Register 00
Address Offset: MBARA + 00h Attribute: R/W
Default Value: 00100241h Size: 32 bit
6.2.2 GBECSR_18—Gigabit Ethernet Capabilities and Status
Register 18
Address Offset: MBARA + 18h Attribute: R/W/SN
Default Value: 01501000h Size: 32 bit
6.2.3 GBECSR_20—Gigabit Ethernet Capabilities and Status
Register 20
Address Offset: MBARA + 20h Attribute: R/W/V
Default Value: 1000XXXXh Size: 32 bit
Bit Description
31:25 Reserved
24 PHY Power Down (PHYPDN) — R/W.
When cleared (0b), the PHY power down setting is controlled by the internal logic of Intel® Xeon®
Processor D-1500 Product Family.
23:0 Reserved
Bit Description
31:21 Reserved
20 PHY Power Down Enable (PHYPDEN) — R/W/SN.
When set, this bit enables the PHY to enter a low-power state when the LAN controller is at the
DMoff/D3 or with no WOL.
19:0 Reserved
Bit Description
31 WAIT — RO.
Set to 1 by the Gigabit Ethernet Controller to indicate that a PCI Express* to SMBus transition is
taking place. The ME/Host should not issue new MDIC transactions while this bit is set to 1. This bit
is auto cleared by HW after the transition has occurred.
30 Error — R/W/V.
Set to 1 by the Gigabit Ethernet Controller when it fails to complete an MDI read. Software should
make sure this bit is clear before making an MDI read or write command.
29 Reserved
28 Ready Bit (RB) — R/W/V.
Set to 1 by the Gigabit Ethernet Controller at the end of the MDI transaction. This bit should be reset
to 0 by software at the same time the command is written.
27:26 MDI Type — R/W/V.
01 = MDI Write
10 = MDI Read
All other values are reserved.
25:21 LAN Connected Device Address (PHYADD) — R/W/V.
20:16 LAN Connected Device Register Address (PHYREGADD) — R/W/V.
15:0 DATA — R/W/V.