Datasheet

Gigabit LAN Configuration Registers
234 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
6.1.26 CLIST2—Capabilities List Register 2 (Gigabit LAN—
D25:F0)
Address Offset: D0h–D1h Attribute: R/WO, RO
Default Value: E005h Size: 16 bits
Function Level Reset: No (Bits 15:8 only)
6.1.27 MCTL—Message Control Register (Gigabit LAN—D25:F0)
Address Offset: D2h–D3h Attribute: R/W, RO
Default Value: 0080h Size: 16 bits
6.1.28 MADDL—Message Address Low Register (Gigabit LAN—
D25:F0)
Address Offset: D4h–D7h Attribute: R/W
Default Value: See bit description Size: 32 bits
6.1.29 MADDH—Message Address High Register (Gigabit LAN—
D25:F0)
Address Offset: D8h–dBh Attribute: R/W
Default Value: See bit description Size: 32 bits
Bit Description
15:8 Next Capability (NEXT) — R/WO. Value of E0h points to the Function Level Reset capability
structure.
These bits are not reset by Function Level Reset.
7:0 Capability ID (CID) — RO. Indicates the linked list item is a Message Signaled Interrupt Register.
Bit Description
15:8 Reserved
7 64-bit Capable (CID) — RO. Set to 1 to indicate that the GbE LAN Controller is capable of
generating 64-bit message addresses.
6:4 Multiple Message Enable (MME) — RO. Returns 000b to indicate that the GbE LAN controller only
supports a single message.
3:1 Multiple Message Capable (MMC) — RO. The GbE LAN controller does not support multiple
messages.
0 MSI Enable (MSIE) — R/W.
0 = MSI generation is disabled.
1 = The Gb LAN controller will generate MSI for interrupt assertion instead of INTx signaling.
Bit Description
31:0 Message Address Low (MADDL) — R/W. Written by the system to indicate the lower 32 bits of the
address to use for the MSI memory write transaction. The lower two bits will always return 0
regardless of the write operation.
Bit Description
31:0 Message Address High (MADDH) — R/W. Written by the system to indicate the upper 32 bits of
the address to use for the MSI memory write transaction.