Datasheet
Gigabit LAN Configuration Registers
232 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
6.1.22 CLIST1—Capabilities List Register 1 (Gigabit LAN—
D25:F0)
Address Offset: C8h–C9h Attribute: RO
Default Value: D001h Size: 16 bits
6.1.23 PMC—PCI Power Management Capabilities Register
(Gigabit LAN—D25:F0)
Address Offset: CAh–CBh Attribute: RO
Default Value: See bit descriptions Size: 16 bits
Function Level Reset:No (Bits 15:11 only)
12:10 Maximum Snoop Latency Scale (MSLS) — R/W. Provides a scale for the value contained within
the Maximum Snoop Latency Value field.
000b = Value times 1 ns
001b = Value times 32 ns
010b = Value times 1,024 ns
011b = Value times 32,768 ns
100b = Value times 1,048,576 ns
101b = Value times 33,554,432 ns
110b-111b – Reserved
9:0 Maximum Snoop Latency (MSL) — R/W. Specifies the maximum snoop latency that a device is
permitted to request. Software should set this to the platform’s maximum supported latency or less.
This field is also an indicator of the platforms maximum latency, should an endpoint send up LTR
Latency Values with the Requirement bit not set.
Bit Description
Bit Description
15:8 Next Capability (NEXT) — RO. Value of D0h indicates the location of the next pointer.
7:0 Capability ID (CID) — RO. Indicates the linked list item is a PCI Power Management Register.
Bit Description
15:11 PME_Support (PMES) — RO. This five-bit field indicates the power states in which the function
may assert PME#. It depend on PM Ena and AUX-PWR bits in word 0Ah in the NVM:
These bits are not reset by Function Level Reset.
10 D2_Support (D2S) — RO. The D2 state is not supported.
9 D1_Support (D1S) — RO. The D1 state is not supported.
8:6 Aux_Current (AC) — RO. Required current defined in the Data Register.
5 Device Specific Initialization (DSI) — RO. Set to 1. The GbE LAN Controller requires its device
driver to be executed following transition to the D0 un-initialized state.
4 Reserved
3 PME Clock (PMEC) — RO. Hardwired to 0.
2:0 Version (VS) — RO. Hardwired to 010b to indicate support for Revision 1.1 of the PCI Power
Management Specification.
Condition Functionality Value
PM Ena=0 No PME at all states 0000b
PM Ena & AUX-PWR=0 PME at D0 and D3hot 01001b
PM Ena & AUX-PWR=1 PME at D0, D3hot and D3cold 11001b