Datasheet

Gigabit LAN Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 231
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
6.1.18 MLMG—Maximum Latency / Minimum Grant Register
(Gigabit LAN—D25:F0)
Address Offset: 3Eh–3Fh Attribute: RO
Default Value: 0000h Size: 16 bits
6.1.19 STCL—System Time Control Low Register (Gigabit LAN—
D25:F0)
Address Offset: A0h–A3h Attribute: RO
Default Value: 00000000h Size: 32 bits
6.1.20 STCH—System Time Control High Register (Gigabit LAN—
D25:F0)
Address Offset: A4h–A7h Attribute: RO
Default Value: 00000000h Size: 32 bits
6.1.21 LTRCAP—System Time Control High Register
(Gigabit LAN—D25:F0)
Address Offset: A8h–ABh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
7:0 Maximum Latency/Minimum Grant (MLMG) — RO. Not used. Hardwired to 00h.
Bit Description
31:0 System Time Control Low (STCL) — RO. Lower 32 bits of the system time capture used for audio
stream synchronization.
Bit Description
31:0 System Time Control High (STCH) — RO. Upper 32 bits of the system time capture used for audio
stream synchronization.
Bit Description
31:29 Reserved
28:26 Maximum Non-Snoop Latency Scale (MNSLS) — R/W. Provides a scale for the value contained
within the Maximum Non-Snoop Latency Value field.
000b = Value times 1 ns
001b = Value times 32 ns
010b = Value times 1,024 ns
011b = Value times 32,768 ns
100b = Value times 1,048,576 ns
101b = Value times 33,554,432 ns
110b-111b – Reserved
25:16 Maximum Non-Snoop Latency (MNSL) — R/W. Specifies the maximum non-snoop latency that a
device is permitted to request. Software should set this to the platform’s maximum supported
latency or less.
This field is also an indicator of the platforms maximum latency, should an endpoint send up LTR
Latency Values with the Requirement bit not set.
15:13 Reserved