Datasheet

Gigabit LAN Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 227
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
6.1.4 PCISTS—PCI Status Register (Gigabit LAN—D25:F0)
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 0010h Size: 16 bits
7 Wait Cycle Control (WCC) — RO. Hardwired to 0.
6 Parity Error Response (PER) — R/W.
0 = Disable.
1 = Indicates that the device is capable of reporting parity errors as a master on the backbone.
5 Palette Snoop Enable (PSE) — RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
3 Special Cycle Enable (SCE) — RO. Hardwired to 0.
2 Bus Master Enable (BME) — R/W.
0 = Disable. All cycles from the device are master aborted
1 = Enable. Allows the root port to forward cycles onto the backbone from a Gigabit LAN* device.
1 Memory Space Enable (MSE) — R/W.
0 = Disable. Memory cycles within the range specified by the memory base and limit registers are
master aborted on the backbone.
1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers
can be forwarded to the Gigabit LAN device.
0 I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disable. I/O cycles within the range specified by the I/O base and limit registers are master
aborted on the backbone.
1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit registers can be
forwarded to the Gigabit LAN device.
Bit Description
Bit Description
15 Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Set when the Gb LAN controller receives a command or data from the backbone with a parity
error. This is set even if PCIMD.PER (D25:F0, bit 6) is not set.
14 Signaled System Error (SSE) — R/WC.
0 = No system error signaled.
1 = Set when the Gb LAN controller signals a system error to the internal SERR# logic.
13 Received Master Abort (RMA) — R/WC.
0 = Root port has not received a completion with unsupported request status from the backbone.
1 = Set when the GbE LAN controller receives a completion with unsupported request status from
the backbone.
12 Received Target Abort (RTA) — R/WC.
0 = Root port has not received a completion with completer abort from the backbone.
1 = Set when the Gb LAN controller receives a completion with completer abort from the backbone.
11 Signaled Target Abort (STA) — R/WC.
0 = No target abort received.
1 = Set whenever the Gb LAN controller forwards a target abort received from the downstream
device onto the backbone.
10:9 DEVSEL# Timing Status (DEV_STS) — RO. Hardwired to 0.
8 Master Data Parity Error Detected (DPED) — R/WC.
0 = No data parity error received.
1 = Set when the Gb LAN Controller receives a completion with a data parity error on the backbone
and PCIMD.PER (D25:F0, bit 6) is set.
7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 0.
6Reserved
5 66 MHz Capable — RO. Hardwired to 0.
4 Capabilities List — RO. Hardwired to 1. Indicates the presence of a capabilities list.