Datasheet

Gigabit LAN Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 225
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
6 Gigabit LAN Configuration
Registers
6.1 Gigabit LAN Configuration Registers
(Gigabit LAN—D25:F0)
Note: Register address locations that are not shown in Ta b l e 6 - 1 should be treated as
Reserved. All GbE registers are located in the VccIOIN power well.
/
Table 6-1. Gigabit LAN Configuration Registers Address Map (Gigabit LAN—D25:F0)
(Sheet 1 of 2)
Offset Mnemonic Register Name Default Attribute
00h–01h VID Vendor Identification 8086h RO
02h–03h DID Device Identification See register
description
RO
04h–05h PCICMD PCI Command 0000h R/W, RO
06h–07h PCISTS PCI Status 0010h R/WC, RO
08h RID Revision Identification See register
description
RO
09h–0Bh CC Class Code 020000h RO
0Ch CLS Cache Line Size 00h R/W
0Dh PLT Primary Latency Timer 00h RO
0Eh HEADTYP Header Type 00h RO
10h–13h MBARA Memory Base Address A 00000000h R/W, RO
14h–17h MBARB Memory Base Address B 00000000h R/W, RO
18h–1Bh MBARC Memory Base Address C 00000001h R/W, RO
2Ch–2Dh SVID Subsystem Vendor ID See register
description
RO
2Eh–2Fh SID Subsystem ID See register
description
RO
30h–33h ERBA Expansion ROM Base Address See register
description
RO
34h CAPP Capabilities List Pointer C8h RO
3Ch–3Dh INTR Interrupt Information See register
description
R/W, RO
3Eh–3Fh MLMG Maximum Latency / Minimum Grant 0000h RO
A0h–A3h STCL System Time Capture Low 00000000h RO
A4h–A7h STCH System Time Capture High 00000000h RO
A8h–ABh LTR Latency Tolerance Reporting 00000000h R/W
C8h–C9h CLIST1 Capabilities List 1 D001h RO
CAh–CBh PMC PCI Power Management Capability See register
description
RO
CCh–CDh PMCS PCI Power Management Control and
Status
See register
description
R/WC, R/W,
RO
CFh DR Data Register See register
description
RO
D0h–D1h CLIST2 Capabilities List 2 E005h R/WO, RO