Datasheet

Chipset Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 223
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.2.1 TIRC0—Thermal Initialization Register C0
Offset Address: C0–C3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.2.2 TIRC4—Thermal Initialization Register C4
Offset Address: C4–C7h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.2.3 TIRC8—Thermal Initialization Register C8
Offset Address: C8–CBh Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.2.4 TIRCC—Thermal Initialization Register CC
Offset Address: CC–CFh Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.2.5 TIRD0—Thermal Initialization Register D0
Offset Address: D0–D3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.2.6 TIRE0—Thermal Initialization Register E0
Offset Address: E0–E3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 R/W. BIOS must program this field to 8000390Bh. No other values are supported.
Bit Description
31:0 R/W. BIOS must program this field to C11F0201h. No other values are supported.
Bit Description
31:0 R/W. BIOS must program this field to 05800000h. No other values are supported.
Bit Description
31:0 R/W. BIOS must program this field to 0000C000h. No other values are supported.
Bit Description
31:0 R/W. BIOS must program this field to 00000320h. No other values are supported.
Bit Description
31:0 R/W. BIOS must program this field to 80001E4Fh. No other values are supported.