Datasheet

Chipset Configuration Registers
222 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.69 CIR3A6C—Chipset Initialization Register 3A6C
Offset Address: 3A6C–3A6Fh Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.70 CIR3A80—Chipset Initialization Register 3A80
Offset Address: 3A80–3A83h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.71 CIR3A84—Chipset Initialization Register 3A84
Offset Address: 3A84–3A87h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.72 CIR3A88—Chipset Initialization Register 3A88
Offset Address: 3A88–3A8Ch Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.2 Thermal Configuration Registers
Note: All registers here are an offset of TBARB (see Section 16.1.19).
Bit Description
31:0 CIR3A6C Field 1 — R/W. BIOS must program this field to 00000001h.
Bit Description
31:0 CIR3A80 Field 1 — R/W. BIOS may program this register.
Bit Description
31:25 Reserved
24 CIR3A84 Field 3 — R/W. BIOS may program this field.
23:19 Reserved
18 CIR3A84 Field 2 — R/W. BIOS may program this field.
17:16 Reserved
15:0 CIR3A84 Field 1 — R/W. BIOS may program this register.
Bit Description
31:1 Reserved
0 CIR3A88 Field 1 — R/W. BIOS may program this field.
Table 5-2. Thermal Initialization Registers
Offset Mnemonic Register Name Default Attribute
C0h-C3h TIRC0 Thermal Initialization Register C0 00000000h R/W
C4h-C7h TIRC4 Thermal Initialization Register C4 00000000h R/W
C8h-CBh TIRC8 Thermal Initialization Register C8 00000000h R/W
CCh-CFh TIRCC Thermal Initialization Register CC 00000000h R/W
D0h-D3h TIRD0 Thermal Initialization Register D0 00000000h R/W
E0h-E3h TIRE0 Thermal Initialization Register E0 00000000h R/W
F0h-F3h TIRF0 Thermal Initialization Register F0 00000000h R/W