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Chipset Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 221
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.65 DISPBDF—Display Bus, Device and Function Initialization
Register
Offset Address: 3424–3427h Attribute: R/W
Default Value: 00040010h Size: 32-bit
5.1.66 FD2—Function Disable 2 Register
Offset Address: 3428–342Bh Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.67 CIR3A28—Chipset Initialization Register 3A28
Offset Address: 3A28–3A2Bh Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.68 CIR3A2C—Chipset Initialization Register 3A2C
Offset Address: 3A2C–3A2Fh Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:19 Reserved.
18:16 Display Target Block (DTB) — R/W. The Target BLK field that Intel® Xeon® Processor D-1500
Product Family South Display controller should use when sending RAVDM messages to the
processor. BIOS must program this field to 110h.
15:8 Display Bus Number (DBN) — R/W. The bus number of the Display in the processor. BIOS must
program this field to 0h.
7:3 Display Device Number (DDN) — R/W. The device number of the Display in the processor.
BIOS must program this field to 2h.
2:0 Display Function Number (DFN) — R/W. The function number of the Display in the processor.
BIOS must program this field to 0h.
Bit Description
31:5 Reserved
4 KT Disable (KTD) —R/W. Default is 0.
0 = Keyboard Text controller (D22:F3) is enabled.
1 = Keyboard Text controller (D22:F3) is Disabled
3 IDE-R Disable (IRERD) —R/W. Default is 0.
0 = IDE Redirect controller (D22:F2) is Enabled.
1 = IDE Redirect controller (D22:F2) is Disabled.
2 Intel
®
MEI #2 Disable (MEI2D) —R/W. Default is 0.
0 = Intel
MEI controller #2 (D22:F1) is enabled.
1 = Intel
MEI controller #2 (D22:F1) is disabled.
1 Intel
MEI #1 Disable (MEI1D) —R/W. Default is 0.
0 = Intel
MEI controller #1 (D22:F0) is enabled.
1 = Intel
MEI controller #1 (D22:F0) is disabled.
0 Display BDF Enable (DBDFEN) —R/W. Default is 0.
Bit Description
31:0 CIR3A28 Field 1 — R/W. BIOS must program this field to 01010000h.
Bit Description
31:0 CIR3A2C Field 1 — R/W. BIOS must program this field to 01010404h.