Datasheet
Chipset Configuration Registers
220 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.64 CG—Clock Gating Register
Offset Address: 341C–341Fh Attribute: R/W
Default Value: 00000000h Size: 32-bit
14 LPC Bridge Disable (LBD) — R/W. Default is 0.
0 = The LPC bridge is enabled.
1 = The LPC bridge is disabled. Unlike the other disables in this register, the following additional
spaces will no longer be decoded by the LPC bridge:
• Memory cycles below 16 MB (1000000h)
• I/O cycles below 64 KB (10000h)
• The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF
Memory cycle in the LPC BIOS range below 4 GB will still be decoded when this bit is set; however,
the aliases at the top of 1 MB (the E and F segment) no longer will be decoded.
13 EHCI #2 Disable (EHCI2D) — R/W. Default is 0.
0 = The EHCI #2 is enabled.
1 = The EHCI #2 is disabled.
12:5 Reserved
4 Intel
®
High Definition Audio Disable (HDAD) — R/W. Default is 0.
0 = The Intel High Definition Audio controller is enabled.
1 = The Intel High Definition Audio controller is disabled and its PCI configuration space is not
accessible.
Note: HD Audio is not supported. This bit will be set to 1.
3 SMBus Disable (SD) — R/W. Default is 0.
0 = The SMBus controller is enabled.
1 = The SMBus controller is disabled. Setting this bit only disables the PCI configuration space.
2 Serial ATA Disable 1 (SAD1) — R/W. Default is 0.
0 = The SATA controller #1 (D31:F2) is enabled.
1 = The SATA controller #1 (D31:F2) is disabled.
1Reserved.
0 BIOS must program this field to 1b.
Bit Description
Bit Description
31 Legacy (LPC) Dynamic Clock Gate Enable — R/W.
0 = Legacy Dynamic Clock Gating is Disabled
1 = Legacy Dynamic Clock Gating is Enabled
30:24 Reserved
23 LAN Static Clock Gating Enable (LANSCGE) — R/W.
0 = LAN Static Clock Gating is Disabled
1 = LAN Static Clock Gating is Enabled when the LAN Disable bit is set in the Backed Up Control
RTC register.
22:17 Reserved
16 PCI Dynamic Gate Enable — R/W.
0 = PCI Dynamic Gating is Disabled
1 = PCI Dynamic Gating is Enabled
15:6 Reserved
5 SMBus Clock Gating Enable (SMBCGEN) — R/W.
0 = SMBus Clock Gating is Disabled.
1 = SMBus Clock Gating is Enabled.
Note: Setting this bit will also clock gate all the TCO logic functionality.
4:0 Reserved