Datasheet

Chipset Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 217
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.61 GCS—General Control and Status Register
Offset Address: 3410–3413h Attribute: R/W, R/WLO
Default Value: 00000yy0h Size: 32-bit
(yy = xx0000x0b)
Bit Description
31:12 Reserved
11:10 Boot BIOS Straps (BBS) — R/W. This field determines the destination of accesses to the BIOS
memory range. The default values for these bits represent the strap values of GPIO51 (bit 11) at
the rising edge of PCH_PWROK and SATA1GP/GPIO19 (bit 10) at the rising edge of PCH_PWROK.
When SPI or LPC is selected, the range that is decoded is further qualified by other configuration
bits described in the respective sections.
The value in this field can be overwritten by software as long as the BIOS Interface Lock-Down
(bit 0) is not set.
Boot BIOS Destination Select to LPC by functional strap or using Boot BIOS Destination Bit will not
affect SPI accesses initiated by Intel Management Engine or Integrated GbE LAN.
9 Server Error Reporting Mode (SERM) — R/W.
0 = Intel® Xeon® Processor D-1500 Product Family is the final target of all errors. The processor
sends a messages to Intel® Xeon® Processor D-1500 Product Family for the purpose of
generating NMI.
1 = The processing unit is the final target of all errors from PCI Express* and internal messages.
In this mode, if Intel® Xeon® Processor D-1500 Product Family detects a fatal, non-fatal, or
correctable error internally or its downstream ports, it sends a message to the processor. If
Intel® Xeon® Processor D-1500 Product Family receives an ERR_* message from the
downstream port, it sends that message to the processing unit.
8:6 Reserved
5 No Reboot (NR) — R/W. This bit is set when the “No Reboot” strap (SPKR pin on Intel® Xeon®
Processor D-1500 Product Family) is sampled high on PCH_PWROK. This bit may be set or cleared
by software if the strap is sampled low but may not override the strap when it indicates “No
Reboot”.
0 = System will reboot upon the second timeout of the TCO timer.
1 = The TCO timer will count down and generate the SMI# on the first timeout, but will not
reboot on the second timeout.
4 Alternate Access Mode Enable (AME) — R/W.
0 = Disabled.
1 = Alternate access read only registers can be written, and write only registers can be read.
Before entering a low power state, several registers from powered down parts may need to
be saved. In the majority of cases, this is not an issue, as registers have read and write
paths. However, several of the ISA compatible registers are either read only or write only. To
get data out of write-only registers, and to restore data into read-only registers, Intel®
Xeon® Processor D-1500 Product Family implements an alternate access mode. For a list of
these registers see Section 3.12.8.
3 Shutdown Policy Select (SPS) — R/W.
0 = Intel® Xeon® Processor D-1500 Product Family will drive INIT# in response to the shutdown
Vendor Defined Message (VDM). (default)
1 = Intel® Xeon® Processor D-1500 Product Family will treat the shutdown VDM similar to
receiving a CF9h I/O write with data value 06h, and will drive PLTRST# active.
Bits 11:10 Description
00b LPC
01b Reserved
10b Reserved
11b SPI