Datasheet
Chipset Configuration Registers
216 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.58 CIR33D4—Chipset Initialization Register 33D4
Offset Address: 33D4–33D7h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.59 RC—RTC Configuration Register
Offset Address: 3400–3403h Attribute: R/W, R/WLO
Default Value: 00000000h Size: 32-bit
5.1.60 HPTC—High Precision Timer Configuration Register
Offset Address: 3404–3407h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31 GPIO_D to PMSYNC Enable (GPIO_D_PMSYNC_EN) — R/W.
0 = GPIO_D (as selected in RCBA+33C8h) pin state not sent to processor over PMSYNC.
1 = GPIO_D state sent to processor over PMSYNC.
30 GPIO_C to PMSYNC Enable (GPIO_C_PMSYNC_EN) — R/W.
0 = GPIO_C (as selected in RCBA+33C8h) pin state not sent to processor over PMSYNC.
1 = GPIO_C state sent to processor over PMSYNC.
29 GPIO_B to PMSYNC Enable (GPIO_B_PMSYNC_EN) — R/W.
0 = GPIO_B (as selected in RCBA+33C8h) pin state not sent to processor over PMSYNC.
1 = GPIO_B state sent to processor over PMSYNC.
28 GPIO_A to PMSYNC Enable (GPIO_A_PMSYNC_EN) — R/W.
0 = GPIO_A (as selected in RCBA+33C8h) pin state not sent to processor over PMSYNC.
1 = GPIO_A state sent to processor over PMSYNC.
27:0 CIR33D4 Field 1 — R/W. BIOS may program this register.
Bit Description
31:5 Reserved
4 Upper 128 Byte Lock (UL) — R/WLO.
0 = Bytes not locked.
1 = Bytes 38h–3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be accessed.
Writes will be dropped and reads will not return any ensured data. Bit reset on system reset.
3 Lower 128 Byte Lock (LL) — R/WLO.
0 = Bytes not locked.
1 = Bytes 38h–3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be accessed.
Writes will be dropped and reads will not return any ensured data. Bit reset on system reset.
2 Upper 128 Byte Enable (UE) — R/W.
0 = Bytes locked.
1 = The upper 128-byte bank of RTC RAM can be accessed.
1:0 Reserved
Bit Description
31:8 Reserved
7 Address Enable (AE) — R/W.
0 = Address disabled.
1 = Intel® Xeon® Processor D-1500 Product Family will decode the High Precision Timer memory
address range selected by bits 1:0 below.
6:2 Reserved
1:0 Address Select (AS) — R/W. This 2-bit field selects 1 of 4 possible memory address ranges for
the High Precision Timer functionality. The encodings are:
00 = FED0_0000h – FED0_03FFh
01 = FED0_1000h – FED0_13FFh
10 = FED0_2000h – FED0_23FFh
11 = FED0_3000h – FED0_33FFh