Datasheet

Chipset Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 215
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.53 CIR33A0—Chipset Initialization Register 33A0
Offset Address: 33A0–33A3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.54 CIR33B0—Chipset Initialization Register 33B0
Offset Address: 33B0–33B3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.55 CIR33C0—Chipset Initialization Register 33C0
Offset Address: 33C0–33C3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.56 PMSYNC_CFG—PMSYNC Configuration
Offset Address: 33C8–33CBh Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.57 CIR33D0—Chipset Initialization Register 33D0
Offset Address: 33D0–33D3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 CIR33A0 Field 1 — R/W. BIOS must program this field to 00000800h.
Bit Description
31:0 CIR33B0 Field 1 — R/W. BIOS must program this field to 00001000h.
Bit Description
31:0 CIR33C0 Field 1 — R/W. BIOS may program this register.
Bit Description
31:12 Reserved
11 GPIO_D Pin Selection (GPIO_D_SEL) — R/W. There are one possible GPIO that this can be
routed to the GPIO_D PMSYNC state. This bit must be set as ‘0b’
0 = GPIO5 (default)
1 = Undefined
10 GPIO_C Pin Selection (GPIO_C_SEL) — R/W. There are two possible GPIOs that can be routed
to the GPIO_C PMSYNC state. This bit selects between them:
0 = GPIO37 (default)
1 = GPIO4
9 GPIO_B Pin Selection (GPIO_B_SEL) — R/W. There are one possible GPIO that this can be
routed to the GPIO_B PMSYNC state. This bit must be set as ‘1b’
0 = Undefined (default)
1 = GPIO37
8 GPIO_A Pin Selection (GPIO_A_SEL) — R/W. There are two possible GPIOs that can be routed
to the GPIO_A PMSYNC state. This bit selects between them:
0 = GPIO4 (default)
1 = GPIO5
7:0 Reserved
Bit Description
31:0 CIR33D0 Field 1 — R/W. BIOS may program this register.