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Chipset Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 213
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.43 DCIR3340—Chipset Initialization Register 3340
Offset Address: 3340–3343h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.44 CIR3344—Chipset Initialization Register 3344
Offset Address: 3344–3347h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.45 CIR3348—Chipset Initialization Register 3348
Offset Address: 3348–334Bh Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.46 CIR3350—Chipset Initialization Register 3350
Offset Address: 3350–3353h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:20 Reserved
19:0 CIR3340 Field 1 — R/W. BIOS may program this register.
Bit Description
31:2 Reserved
1:0 CIR3344 Field 1 — R/W. BIOS must program this field to 10b.
Bit Description
31:8 Reserved
7 CIR3348 Field 8 — R/W. BIOS may program this field for PCIe port 8.
6 CIR3348 Field 7 — R/W. BIOS may program this field for PCIe port 7.
5 CIR3348 Field 6 — R/W. BIOS may program this field for PCIe port 6.
4 CIR3348 Field 5 — R/W. BIOS may program this field for PCIe port 5.
3 CIR3348 Field 4 — R/W. BIOS may program this field for PCIe port 4.
2 CIR3348 Field 3 — R/W. BIOS may program this field for PCIe port 3.
1 CIR3348 Field 2 — R/W. BIOS may program this field for PCIe port 2.
0 CIR3348 Field 1 — R/W. BIOS may program this field for PCIe port 1.
Bit Description
31:8 Reserved
7 CIR3350 Field 8 — R/W. BIOS may program this field for PCIe port 8.
6 CIR3350 Field 7 — R/W. BIOS may program this field for PCIe port 7.
5 CIR3350 Field 6 — R/W. BIOS may program this field for PCIe port 6.
4 CIR3350 Field 5 — R/W. BIOS may program this field for PCIe port 5.
3 CIR3350 Field 4 — R/W. BIOS may program this field for PCIe port 4.
2 CIR3350 Field 3 — R/W. BIOS may program this field for PCIe port 3.
1 CIR3350 Field 2 — R/W. BIOS may program this field for PCIe port 2.
0 CIR3350 Field 1 — R/W. BIOS may program this field for PCIe port 1.