Datasheet

Chipset Configuration Registers
212 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.42 CIR3324—Chipset Initialization Register 3324
Offset Address: 3324–3327h Attribute: R/W
Default Value: 00000000h Size: 32-bit
17:16 SLP_A# Minimum Assertion Width (SLP_A_MIN_ASST_WDTH) — R/W. This field indicates
the minimum assertion width of the SLP_A# signal to guarantee that the VCCIOIN supplies have
been fully power cycled. This value may be modified per platform depending on power supply
capacitance, board capacitance, power circuits, and so on.
Valid values are:
11 = 2 seconds
10 = 98 ms
01 = 4 seconds
00 = 0 ms (that is, stretching disabled – default)
These bits are cleared by RTCRST# assertion.
Notes:
1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.
2. This field is ignored when exiting G3 states if the “Disable SLP Stretching After SUS Well
Power Up” bit is set.
15:14 SLP_LAN# Minimum Assertion Width (SLP_LAN_MIN_ASST_WDTH) — R/WL. This field
indicates the minimum assertion width of the SLP_LAN# signal to guarantee that the PHY power
supplies have been fully power cycled. This value may be modified per platform depending on
power supply capacitance, board capacitance, power circuits, and so on.
Valid values are:
11 = 2 seconds
10 = 50 ms
01 = 1 ms
00 = 0 ms (that is, stretching disabled – default)
These bits are cleared by RTCRST# assertion.
Note: This field is RO when the SLP Stretching Policy Lock-Down bit is set.
13:10 Reserved
9:8 Reset Power Cycle Duration (PWR_CYC_DUR) — R/WL. This field indicates the minimum time
a platform will stay in reset (SLP_S3#, SLP_S4#, SLP_S5# asserted and SLP_A# and SLP_LAN#
asserted if applicable) during a host reset with power cycle, host reset with power down or a
global reset. The duration programmed in this register takes precedence over the applicable
SLP_# stretch timers in these reset scenario.
Valid values are:
11 = 1-2 seconds
10 = 2-3 seconds
01 = 3-4 seconds
00 = 4-5 seconds (default)
These bits are cleared by RTCRST# assertion.
Notes:
1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.
2. The duration programmed in this register should never be smaller than the stretch duration
programmed in the following registers:
— GEN_PMCON_3.SLP_S3_MIN_ASST_WDTH
— GEN_PMCON_3.SLP_S4_MIN_ASST_WDTH
— PM_CFG.SLP_A_MIN_ASST_WDTH
— PM_CFG.SLP_LAN_MIN_ASST_WDTH
7:5 Reserved
4 Host Wireless LAN PHY Power Enable (HOST_WLAN_PP_EN) - R/W.
Set by host software when it desires the WiFi LAN PHY to be powered in Sx power states for Wake
Over WiFi (WoWLAN). See SLP_WLAN# for more information. Default = 0b.
3:0 Reserved
Bit Description
Bit Description
31:0 CIR3324 Field 1 — R/W. BIOS must program this field to 04000000h.