Datasheet

Chipset Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 211
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.40 CIR3314—Chipset Initialization Register 3314
Offset Address: 3314–3317h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.41 PM_CFG—Power Management Configuration Register
Offset Address: 3318–331Bh Attribute: R/W
Default Value: 00000020h Size: 32-bit
5 Wake On LAN Override Wake Status (WOL_OVR_WK_STS) — R/WC. This bit gets set when
all of the following conditions are met:
• Integrated LAN Signals a Power Management Event
• The system is not in S0
• The “WoL Enable Override” bit is set in configuration space.
BIOS can read this status bit to determine this wake source.
Software clears this bit by writing a 1 to it.
4 PRSTS Field 1 — R/WC. BIOS may program this field.
3 Intel ME Host Power Down (ME_HOST_PWRDN) — R/WC. This bit is set when the Intel
Management Engine generates a host reset with power down.
2 Intel ME Host Reset Warm Status (ME_HRST_WARM_STS) — R/WC. This bit is set when the
Intel Management Engine generates a Host reset without power cycling. Software clears this bit by
writing a 1 to this bit position.
1 Intel ME Host Reset Cold Status (ME_HRST_COLD_STS) — R/WC. This bit is set when the
Intel Management Engine generates a Host reset with power cycling. Software clears this bit by
writing a 1 to this bit position.
0 Intel ME WAKE STATUS (ME_WAKE_STS) — R/WC. This bit is set when the Intel Management
Engine generates a Non-Maskable wake event, and is not affected by any other enable bit. When
this bit is set, the Host Power Management logic wakes to S0.
Bit Description
Bit Description
31:11 Reserved
10:0 CIR3314 Field 1— R/W. BIOS may write to this field.
Bit Description
31:27 Reserved
26:24 PM_CFG Field 1 — R/W. BIOS must program this field to 101b.
23:20 Reserved
19:18 SLP_SUS# Minimum Assertion Width (SLP_SUS_MIN_ASST_WDTH)— R/WL. This field
indicates the minimum assertion width of the SLP_SUS# signal to guarantee that the SUS power
supplies have been fully power cycled. This value may be modified per platform depending on
power supply capacitance, board capacitance, power circuits, and so on.
Valid values are:
11 = 4 seconds
10 = 1 second
01 = 500 ms
00 = 0 ms (that is, stretching disabled - default)
These bits are cleared by RTCRST# assertion.
Notes:
1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.
2. This field is ignored when exiting G3 states if the “Disable SLP Stretching After SUS Well
Power Up” bit is set. Unlike with all other SLP_* pin stretching, this disable bit only impacts
SLP_SUS# stretching during G3 exit, rather than both G3 exit.