Datasheet

Chipset Configuration Registers
208 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.34 OIC—Other Interrupt Control Register
Offset Address: 31FE–31FFh Attribute: R/W
Default Value: 0000h Size: 16-bit
14:12 Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on Intel® Xeon® Processor
D-1500 Product Family is connected to the INTD# pin reported for device 20 functions:
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
3h = PIRQD# (Default)
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
11 Reserved
10:8 Interrupt C Pin Route (ICR) — R/W. Indicates which physical pin on Intel® Xeon® Processor
D-1500 Product Family is connected to the INTC# pin reported for device 20 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
7Reserved
6:4 Interrupt B Pin Route (IBR) — R/W. Indicates which physical pin on Intel® Xeon® Processor
D-1500 Product Family is connected to the INTB# pin reported for device 20 functions.
0h = PIRQA#
1h = PIRQB# (Default)
2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
3Reserved
2:0 Interrupt A Pin Route (IAR) — R/W. Indicates which physical pin on Intel® Xeon® Processor
D-1500 Product Family is connected to the INTA# pin reported for device 20 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
Bit Description
Bit Description
15:10 Reserved
9 Coprocessor Error Enable (CEN) — R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = If FERR# is low, Intel® Xeon® Processor D-1500 Product Family generates IRQ13 internally
and holds it until an I/O port F0h write. It will also drive IGNNE# active.
8 APIC Enable (AEN) — R/W.
0 = The internal IOxAPIC is disabled.
1 = Enables the internal IOxAPIC and its address decode.
Note: Software should read this register after modifying APIC enable bit prior to access to the
IOxAPIC address range.