Datasheet

Chipset Configuration Registers
202 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.26 D30IR—Device 30 Interrupt Route Register
Offset Address: 3142–3143h Attribute: RO
Default Value: 0000h Size: 16-bit
5.1.27 D29IR—Device 29 Interrupt Route Register
Offset Address: 3144–3145h Attribute: R/W
Default Value: 3210h Size: 16-bit
14:12 Interrupt D Pin Route (IDR) — R/W. Indicates which physical pin on Intel® Xeon® Processor
D-1500 Product Family is connected to the INTD# pin reported for device 31 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
3h = PIRQD# (Default)
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
11 Reserved
10:8 Interrupt C Pin Route (ICR) — R/W. Indicates which physical pin on Intel® Xeon® Processor
D-1500 Product Family is connected to the INTC# pin reported for device 31 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
7Reserved
6:4 Interrupt B Pin Route (IBR) — R/W. Indicates which physical pin on Intel® Xeon® Processor
D-1500 Product Family is connected to the INTB# pin reported for device 31 functions.
0h = PIRQA#
1h = PIRQB# (Default)
2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
3Reserved
2:0 Interrupt A Pin Route (IAR) — R/W. Indicates which physical pin on Intel® Xeon® Processor
D-1500 Product Family is connected to the INTA# pin reported for device 31 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
Bit Description
Bit Description
15:0 Reserved. No interrupts generated from Device 30.
Bit Description
15 Reserved