Datasheet

Chipset Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 201
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.23 D22IP—Device 22 Interrupt Pin Register
Offset Address: 3124–3127h Attribute: R/W
Default Value: 00004321h Size: 32-bit
5.1.24 D20IP—Device 20 Interrupt Pin Register
Offset Address: 3128–312bh Attribute: R/W
Default Value: 00000021h Size: 32-bit
5.1.25 D31IR—Device 31 Interrupt Route Register
Offset Address: 3140–3141h Attribute: R/W
Default Value: 3210h Size: 16-bit
Bit Description
31:16 Reserved
15:12 KT Pin (KTIP) — R/W. Indicates which pin the Keyboard text PCI functionality drives as its
interrupt
0h = No Interrupt
1h = INTA#
2h = INTB#
3h = INTC#
4h = INTD# (Default)
5h–Fh = Reserved
11:8 IDE-R Pin (IDERIP) — R/W. Indicates which pin the IDE Redirect PCI functionality drives as its
interrupt
0h = No Interrupt
1h = INTA#
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–Fh = Reserved
7:4 Intel
®
MEI #2 Pin (MEI2IP) — R/W. Indicates which pin the Management Engine Interface #2
drives as its interrupt
0h = No Interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
3:0 Intel
®
MEI #1 Pin (MEI1IP) — R/W. Indicates which pin the Management Engine Interface
controller #1 drives as its interrupt
0h = No Interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Bit Description
31:4 Reserved
3:0 xHCI Pin (XHCIIP) — R/W. Indicates which pin the xHCI drives as its interrupt
0h = No Interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Bit Description
15 Reserved