Datasheet

Chipset Configuration Registers
200 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.20 D27IP—Device 27 Interrupt Pin Register
Offset Address: 3110–3113h Attribute: R/W
Default Value: 00000001h Size: 32-bit
5.1.21 D26IP—Device 26 Interrupt Pin Register
Offset Address: 3114–3117h Attribute: R/W
Default Value: 30000321h Size: 32-bit
5.1.22 D25IP—Device 25 Interrupt Pin Register
Offset Address: 3118–311Bh Attribute: R/W
Default Value: 00000001h Size: 32-bit
7:4 PCI Express #2 Pin (P2IP) — R/W. Indicates which pin the PCI Express port #2 drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–7h = Reserved
3:0 PCI Express #1 Pin (P1IP) — R/W. Indicates which pin the PCI Express port #1 drives as its
interrupt.
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–7h = Reserved
Bit Description
Bit Description
31:0 Reserved
Bit Description
31:4 Reserved
3:0 EHCI #2 Pin (E2P) — R/W. Indicates which pin EHCI controller #2 drives as its interrupt, if
controller exists.
0h = No Interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserve
Note: EHCI Controller #2 is mapped to Device 26 Function 0.
Bit Description
31:4 Reserved
3:0 GbE LAN Pin (LIP) — R/W. Indicates which pin the internal GbE LAN controller drives as its
interrupt
0h = No Interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved