Datasheet

Chipset Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 199
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.19 D28IP—Device 28 Interrupt Pin Register
Offset Address: 310C–310Fh Attribute: R/W
Default Value: 00214321h Size: 32-bit
3:0 EHCI #1 Pin (E1P) — R/W. Indicates which pin the EHCI controller #1 drives as its interrupt, if
controller exists.
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–7h = Reserved
Note: EHCI Controller #1 is mapped to Device 29 Function 0.
Bit Description
Bit Description
31:28 PCI Express* #8 Pin (P8IP) — R/W. Indicates which pin the PCI Express* port #8 drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB#
3h = INTC#
4h = INTD# (Default)
5h–7h = Reserved
27:24 PCI Express #7 Pin (P7IP) — R/W. Indicates which pin the PCI Express port #7 drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–7h = Reserved
23:20 PCI Express* #6 Pin (P6IP) — R/W. Indicates which pin the PCI Express* port #6 drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–7h = Reserved
19:16 PCI Express #5 Pin (P5IP) — R/W. Indicates which pin the PCI Express port #5 drives as its
interrupt.
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–7h = Reserved
15:12 PCI Express #4 Pin (P4IP) — R/W. Indicates which pin the PCI Express* port #4 drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB#
3h = INTC#
4h = INTD# (Default)
5h–7h = Reserved
11:8 PCI Express #3 Pin (P3IP) — R/W. Indicates which pin the PCI Express port #3 drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–7h = Reserved