Datasheet

Chipset Configuration Registers
198 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.16 D31IP—Device 31 Interrupt Pin Register
Offset Address: 3100–3103h Attribute: R/W, RO
Default Value: 03243200h Size: 32-bit
5.1.17 D30IP—Device 30 Interrupt Pin Register
Offset Address: 3104–3107h Attribute: RO
Default Value: 00000000h Size: 32-bit
5.1.18 D29IP—Device 29 Interrupt Pin Register
Offset Address: 3108–310Bh Attribute: R/W
Default Value: 10004321h Size: 32-bit
Bit Description
31:28 Reserved
27:24 Thermal Throttle Pin (TTIP) — R/W. Indicates which pin the Thermal Throttle controller drives
as its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–Fh = Reserved
23:20 SATA Pin 2 (SIP2) — R/W. Indicates which pin the SATA controller 2 drives as its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
19:16 Reserved
15:12 SMBus Pin (SMIP) — R/W. Indicates which pin the SMBus controller drives as its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–Fh = Reserved
11:8 SATA Pin (SIP) — R/W. Indicates which pin the SATA controller drives as its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
7:4 Reserved
3:0 LPC Bridge Pin (LIP) — RO. Currently, the LPC bridge does not generate an interrupt, so this
field is read-only and 0h.
Bit Description
31:0 Reserved
Bit Description
31:4 Reserved