Datasheet

Chipset Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 197
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.12 REC—Root Error Command Register
Offset Address: 20AC–20AFh Attribute: R/W
Default Value: 0000h Size: 32-bit
5.1.13 CIR2314—Chipset Initialization Register 2314
Offset Address: 2314–2317h Attribute: R/W
Default Value: 0A000000h Size: 32-bit
5.1.14 CIR2320—Chipset Initialization Register 2320
Offset Address: 2320–2323h Attribute: R/W
Default Value: 00000000h Size: 32-bit
5.1.15 TCTL—TCO Configuration Register
Offset Address: 3000h Attribute: R/W
Default Value: 00h Size: 8-bit
Bit Description
31 Drop Poisoned Downstream Packets (DPDP) — R/W. Determines how downstream packets
for internal messaging are handled that are received with the EP field set, indicating poisoned
data:
0 = Packets are forwarded downstream without forcing the UT field set.
1 = This packet and all subsequent packets with data received internally for any VC will have
their Unsupported Transaction (UT) field set causing them to master Abort downstream.
Packets without data such as memory, I/O and config read requests are allowed to proceed.
30:0 Reserved
Bit Description
31:0 CIR2314 Field 1 — R/W. BIOS may program this field.
Bit Description
31:0 CIR2320 Field 1 — R/W. BIOS may program this field.
Bit Description
7 TCO IRQ Enable (IE) — R/W.
0 = TCO IRQ is disabled.
1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field.
6:3 Reserved
2:0 TCO IRQ Select (IS) — R/W. Specifies on which IRQ the TCO will internally appear. If not using
the APIC, the TCO interrupt must be routed to IRQ9–11, and that interrupt is not sharable with
the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the TCO
interrupt can also be mapped to IRQ20–23, and can be shared with other interrupt.
000 = IRQ 9
001 = IRQ 10
010 = IRQ 11
011 = Reserved
100 = IRQ 20 (only if APIC enabled)
101 = IRQ 21 (only if APIC enabled)
110 = IRQ 22 (only if APIC enabled)
111 = IRQ 23 (only if APIC enabled)
When setting the these bits, the IE bit should be cleared to prevent glitching.
When the interrupt is mapped to APIC interrupts 9, 10, or 11, the APIC should be programmed for
active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC
should be programmed for active-low reception.