Datasheet

Chipset Configuration Registers
196 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.9 V0STS—Virtual Channel 0 Resource Status Register
Offset Address: 201A–201Bh Attribute: RO
Default Value: 0000h Size: 16-bit
5.1.10 V1CTL—Virtual Channel 1 Resource Control Register
Offset Address: 2020–2023h Attribute: R/W, RO, R/WL
Default Value: 00000000h Size: 32-bit
5.1.11 V1STS—Virtual Channel 1 Resource Status Register
Offset Address: 2026–2027h Attribute: RO
Default Value: 0000h Size: 16-bit
26:24 Virtual Channel Identifier (ID) — RO. Indicates the ID to use for this virtual channel.
23:16 Reserved
15:10 Extended TC/VC Map (ETVM)— R/WL. Defines the upper 8-bits of the VC0 16-bit TC/VC
mapping registers. These registers use the PCI Express reserved TC[3] traffic class bit. These bits
are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set.
9:7 Reserved
6:1 Transaction Class / Virtual Channel Map (TVM) — R/WL. Indicates which transaction classes
are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the
virtual channel. These bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set.
0Reserved
Bit Description
Bit Description
15:2 Reserved
1 VC Negotiation Pending (NP) — RO. When set, this bit indicates the virtual channel is still
being negotiated with ingress ports.
0Reserved
Bit Description
31 Virtual Channel Enable (EN) — R/W. Enables the VC when set. Disables the VC when cleared.
30:28 Reserved
27:24 Virtual Channel Identifier (ID) — R/W. Indicates the ID to use for this virtual channel.
23:16 Reserved
15:10 Extended TC/VC Map (ETVM) — R/WL. Defines the upper 8-bits of the VC0 16-bit TC/VC
mapping registers. These registers use the PCI Express* reserved TC[3] traffic class bit. These
bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set.
9:8 Reserved
7:1 Transaction Class / Virtual Channel Map (TVM) — R/WL. Indicates which transaction classes
are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the
virtual channel. These bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set.
0Reserved
Bit Description
15:2 Reserved
1 VC Negotiation Pending (NP) — RO. When set, this bit indicates the virtual channel is still
being negotiated with ingress ports.
0Reserved