Datasheet

Chipset Configuration Registers
Intel® Xeon® Processor D-1500 Product Family 195
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.6 TWDR—Trapped Write Data Register
Offset Address: 1E18–1E1Fh Attribute: RO
Default Value: 0000000000000000h Size: 64-bit
This register saves the data from I/O write cycles that are trapped for software to read.
5.1.7 IOTRn—I/O Trap Register (0–3)
Offset Address: 1E80–1E87h Register 0 Attribute: R/W
1E88–1E8Fh Register 1
1E90–1E97h Register 2
1E98–1E9Fh Register 3
Default Value: 0000000000000000h Size: 64-bit
These registers are used to specify the set of I/O cycles to be trapped and to enable
this functionality.
5.1.8 V0CTL—Virtual Channel 0 Resource Control Register
Offset Address: 2014–2017h Attribute: R/WL, RO
Default Value: 80000010h Size: 32-bit
Bit Description
63:32 Reserved
31:0 Trapped I/O Data (TIOD) — RO. DWord of I/O write data. This field is undefined after trapping
a read cycle.
Bit Description
63:50 Reserved
49 Read/Write Mask (RWM) — R/W.
0 = The cycle must match the type specified in bit 48.
1 = Trapping logic will operate on both read and write cycles.
48 Read/Write# (RWIO) — R/W.
0 = Write
1 = Read
Note: The value in this field does not matter if bit 49 is set.
47:40 Reserved
39:36 Byte Enable Mask (BEM) — R/W. A 1 in any bit position indicates that any value in the
corresponding byte enable bit in a received cycle will be treated as a match. The corresponding bit
in the Byte Enables field, below, is ignored.
35:32 Byte Enables (TBE) — R/W. Active-high DWord-aligned byte enables.
31:24 Reserved
23:18 Address[7:2] Mask (ADMA) — R/W. A 1 in any bit position indicates that any value in the
corresponding address bit in a received cycle will be treated as a match. The corresponding bit in
the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord
address, allowing for traps on address ranges up to 256 bytes in size.
17:16 Reserved
15:2 I/O Address[15:2] (IOAD) — R/W. DWord-aligned address
1 Reserved
0 Trap and SMI# Enable (TRSE) — R/W.
0 = Trapping and SMI# logic disabled.
1 = The trapping logic specified in this register is enabled.
Bit Description
31 Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and cannot be
disabled.
30:27 Reserved