Datasheet

Chipset Configuration Registers
194 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.3 FLRSTAT—Function Level Reset Pending Status Register
Offset Address: 0408–040Bh Attribute: RO/V
Default Value: 00000000h Size: 32-bit
5.1.4 TRSR—Trap Status Register
Offset Address: 1E00–1E03h Attribute: R/WC, RO
Default Value: 00000000h Size: 32-bit
5.1.5 TRCR—Trapped Cycle Register
Offset Address: 1E10–1E17h Attribute: RO
Default Value: 0000000000000000h Size: 64-bit
This register saves information about the I/O Cycle that was trapped and generated the
SMI# for software to read.
Bit Description
31:24 Reserved
23 FLR Pending Status for D29:F0, EHCI #1 — RO/V.
0 = Function Level Reset is not pending.
1 = Function Level Reset is pending.
22:16 Reserved
15 FLR Pending Status for D26:F0, EHCI #2 — RO/V.
0 = Function Level Reset is not pending.
1 = Function Level Reset is pending.
14:0 Reserved
Bit Description
31:4 Reserved
3:0 Cycle Trap SMI# Status (CTSS) — R/WC. These bits are set by hardware when the
corresponding Cycle Trap register is enabled and a matching cycle is received (and trapped).
These bits are OR’ed together to create a single status bit in the Power Management register
space.
The SMI# and trapping must be enabled in order to set these bits.
These bits are set before the completion is generated for the trapped cycle, thereby ensuring that
the processor can enter the SMI# handler when the instruction completes. Each status bit is
cleared by writing a 1 to the corresponding bit location in this register.
Bit Description
63:25 Reserved
24 Read/Write# (RWI) — RO.
0 = Trapped cycle was a write cycle.
1 = Trapped cycle was a read cycle.
23:20 Reserved
19:16 Active-high Byte Enables (AHBE) — RO. This is the DWord-aligned byte enables associated
with the trapped cycle. A 1 in any bit location indicates that the corresponding byte is enabled in
the cycle.
15:2 Trapped I/O Address (TIOA) — RO. This is the DWord-aligned address of the trapped cycle.
1:0 Reserved