Datasheet
Chipset Configuration Registers
192 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5.1.1 RPC—Root Port Configuration Register
Offset Address: 0400–0403h Attribute: R/W, RO
Default Value: 0000000yh (y = 00xxb) Size: 32-bit
5.1.2 RPFN—Root Port Function Number and Hide for PCI
Express* Root Ports Register
Offset Address: 0404–0407h Attribute: R/W, R/WO
Default Value: 76543210h Size: 32-bit
For the PCI Express root ports, the assignment of a function number to a root port is
not fixed. BIOS may re-assign the function numbers on a port by port basis. This
capability will allow BIOS to disable/hide any root port and still have functions 0 thru N-
1 where N is the total number of enabled root ports.
Port numbers will remain fixed to a physical root port.
3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W
3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W
3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W
3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W
314Ch–314Dh D26IR Device 26 Interrupt Route 3210h R/W
3150h–3151h D25IR Device 25 Interrupt Route 3210h R/W
315Ch–315Dh D22IR Device 22 Interrupt Route 3210h R/W
3160h–3161h D20IR Device 20 Interrupt Route 3210h R/W
31FEh–31FFh OIC Other Interrupt Control 0000h R/W
3300h–3303h WADT_AC Wake Alarm Device Timer – AC FFFFFFFFh R/W
3304h–3307h WADT_DC Wake Alarm Device Timer – DC FFFFFFFFh R/W
3308h–330Bh WADT_EXP_AC Wake Alarm Device Expired Timer – AC FFFFFFFFh R/W
330Ch–330Fh WADT_EXP_DC Wake Alarm Device Expired Timer – DC FFFFFFFFh R/W
3310h–3313h PRSTS Power and Reset Status 05000000h RO, R/WC
3318h–331Bh PM_CFG Power Management Configuration 00000020h R/W
33C8h–33CBh PMSYNC_CFG PMSYNC Configuration 00000000h R/W
3400h–3403h RC RTC Configuration 00000000h R/W,
R/WLO
3404h–3407h HPTC High Precision Timer Configuration 00000000h R/W
3410h–3413h GCS General Control and Status 000000yy0h R/W,
R/WLO
3414h BUC Backed Up Control 00h R/W
3418h–341Bh FD Function Disable 00000000h R/W
341Ch–341Fh CG Clock Gating 00000000h R/W
3424h–3425h DISPBDF Display Bus, Device and Function Initialization 00040010h R/W
3428h–342Bh FD2 Function Disable 2 00000000h R/W
Table 5-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Attribute
Bit Description
31:0 Reserved. BIOS may write to this register, as needed.