Datasheet

190 Intel® Xeon® Processor D-1500 Product Family

Datasheet - Volume 1 of 4: Integrated Platform Controller Hub

March 2015

The scheme is based on the concept that the top block is reserved as the “boot” block,

and the block immediately below the top block is reserved for doing boot-block

updates.

The algorithm is:

1. Software copies the top block to the block immediately below the top

2. Software checks that the copied block is correct. This could be done by performing

a checksum calculation.

3. Software sets the Top Swap bit. This will invert the appropriate address bits for the

cycles going to the FWH or SPI.

4. Software erases the top block

5. Software writes the new top block

6. Software checks the new top block

7. Software clears the Top Swap bit

If a power failure occurs at any point after step 3, the system will be able to boot from

the copy of the boot-block that is stored in the block below the top. This is because the

Top Swap bit is backed in the RTC well.

Note: The “Top Swap” mode may be forced by an external strapping option. When top swap

mode is forced in this manner, the Top Swap bit cannot be cleared by software. A re-

boot with the strap removed will be required to exit a forced top-block swap mode.

Note: Top swap mode only affects accesses to the Firmware Hub space, not feature space for

FWH.

Note: The top swap mode has no effect on accesses below FFFE_0000h for FWH.