Datasheet

Register and Memory Mapping
Intel® Xeon® Processor D-1500 Product Family 189
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Notes:
1. Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High Precision Event Timers. If attempted,
the lock is not honored, which means potential deadlock conditions may occur.
2. PCI is the target when the Boot BIOS Destination selection bits are set to 10b (Chipset Config Registers:Offset 3401 bits
11:10). When PCI selected, the Firmware Hub Decode Enable bits have no effect.
4.4.1 Boot-Block Update Scheme
Intel® Xeon® Processor D-1500 Product Family supports a “Top Swap” mode that has
Intel® Xeon® Processor D-1500 Product Family swap the top block in the FWH or SPI
flash (the boot-block) with another location. This allows for safe update of the boot-
block (even if a power failure occurs). When the “Top Swap” Enable bit is set, Intel®
Xeon® Processor D-1500 Product Family will invert A16 for cycles going to the upper
two 64 KB blocks in the FWH or appropriate address lines as selected in BIOS Boot-
Block size soft strap for SPI.
Specifically for FHW, in this mode accesses to FFFF_0000h–FFFF_FFFFh are directed to
FFFE_0000h–FFFE_FFFFh and vice versa. When the Top Swap Enable bit is 0, Intel®
Xeon® Processor D-1500 Product Family will not invert A16.
Specifically for SPI, in this mode the “Top Swap” behavior is as described below. When
the Top Swap Enable bit is 0, Intel® Xeon® Processor D-1500 Product Family will not
invert any address bit.
This bit is automatically set to 0 by RTCRST#, but not by PLTRST#.
2 KB anywhere above 64 KB to
4 GB range
SATA Host Controller #1 AHCI memory-mapped registers. Enable using standard PCI
mechanism (D31:F2)
Memory Base/Limit anywhere in
4 GB range
PCI Express* Root Ports 1-8 Enable using standard PCI mechanism (D28: F 0-7)
Prefetchable Memory Base/Limit
anywhere in 64-bit address range
PCI Express Root Ports 1-8 Enable using standard PCI mechanism (D28:F 0-7)
4 KB anywhere in 64-bit address
range
Thermal Reporting Enable using standard PCI mechanism (D31:F6 TBAR/
TBARH)
4 KB anywhere in 64-bit address
range
Thermal Reporting Enable using standard PCI mechanism (D31:F6 TBARB/
TBARBH)
16 Bytes anywhere in 64-bit
address range
Intel
®
MEI #1, #2 Enable using standard PCI mechanism (D22:F 1:0)
4 KB anywhere in 4 GB range KT Enable using standard PCI mechanism (D22:F3)
16 KB anywhere in 4 GB range Root Complex Register Block
(RCRB)
Enable using setting bit[0] of the Root Complex Base
Address register (D31:F0:offset F0h).
Table 4-4. Memory Decode Ranges from Processor Perspective (Sheet 3 of 3)
Memory Range Target Dependency/Comments
Table 4-5. SPI Mode Address Swapping
BIOS Boot-Block size
Value
Accesses to Being Directed to
000 (64 KB) FFFF_0000h–FFFF_FFFFh FFFE_0000h–FFFE_FFFFh and vice versa
001 (128 KB) FFFE_0000h–FFFF_FFFFh FFFC_0000h–FFFD_FFFFh and vice versa
010 (256 KB) FFFC_0000h–FFFF_FFFFh FFF8_0000h–FFFB_FFFFh and vice versa
011 (512 KB) FFF8_0000h–FFFF_FFFFh FFF0_0000h–FFF7_FFFFh and vice versa
100 (1 MB) FFF0_0000h–FFFF_FFFFh FFE0_0000h–FFEF_FFFFh and vice versa
101–111 Reserved Reserved