Datasheet

Register and Memory Mapping
188 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
FEC1 8000h–FEC1 FFFFh PCI Express* Port 2 PCI Express* Root Port 2 I/OxAPIC Enable (PAE) set
FEC2 0000h–FEC2 7FFFh PCI Express* Port 3 PCI Express* Root Port 3 I/OxAPIC Enable (PAE) set
FEC2 8000h–FEC2 FFFFh PCI Express* Port 4 PCI Express* Root Port 4 I/OxAPIC Enable (PAE) set
FEC3 0000h–FEC3 7FFFh PCI Express* Port 5 PCI Express* Root Port 5 I/OxAPIC Enable (PAE) set
FEC3 8000h–FEC3 FFFFh PCI Express* Port 6 PCI Express* Root Port 6 I/OxAPIC Enable (PAE) set
FEC4 0000h–FEC4 7FFF PCI Express* Port 7 PCI Express* Root Port 7 I/OxAPIC Enable (PAE) set
FEC4 8000h–FEC4 FFFF PCI Express* Port 8 PCI Express* Root Port 8 I/OxAPIC Enable (PAE) set
FFC0 0000h–FFC7 FFFFh
FF80 0000h–FF87 FFFFh
LPC or SPI (or PCI)
2
Bit 8 in BIOS Decode Enable register is set
FFC8 0000h–FFCF FFFFh
FF88 0000h–FF8F FFFFh
LPC or SPI (or PCI)
2
Bit 9 in BIOS Decode Enable register is set
FFD0 0000h–FFD7 FFFFh
FF90 0000h–FF97 FFFFh
LPC or SPI (or PCI)
2
Bit 10 in BIOS Decode Enable register is set
FFD8 0000h–FFDF FFFFh
FF98 0000h–FF9F FFFFh
LPC or SPI (or PCI)
2
Bit 11 in BIOS Decode Enable register is set
FFE0 000h–FFE7 FFFFh
FFA0 0000h–FFA7 FFFFh
LPC or SPI (or PCI)
2
Bit 12 in BIOS Decode Enable register is set
FFE8 0000h–FFEF FFFFh
FFA8 0000h–FFAF FFFFh
LPC or SPI (or PCI)
2
Bit 13 in BIOS Decode Enable register is set
FFF0 0000h–FFF7 FFFFh
FFB0 0000h–FFB7 FFFFh
LPC or SPI (or PCI)
2
Bit 14 in BIOS Decode Enable register is set
FFF8 0000h–FFFF FFFFh
FFB8 0000h–FFBF FFFFh
LPC or SPI (or PCI)
2
Always enabled.
The top two 64 KB blocks of this range can be swapped, as
described in Section 4.4.1.
FF70 0000h–FF7F FFFFh
FF30 0000h–FF3F FFFFh
LPC or SPI (or PCI)
2
Bit 3 in BIOS Decode Enable register is set
FF60 0000h–FF6F FFFFh
FF20 0000h–FF2F FFFFh
LPC or SPI (or PCI)
2
Bit 2 in BIOS Decode Enable register is set
FF50 0000h–FF5F FFFFh
FF10 0000h–FF1F FFFFh
LPC or SPI (or PCI)
2
Bit 1 in BIOS Decode Enable register is set
FF40 0000h–FF4F FFFFh
FF00 0000h–FF0F FFFFh
LPC or SPI (or PCI)
2
Bit 0 in BIOS Decode Enable register is set
128 KB anywhere in 4 GB range Integrated LAN Controller Enable using BAR in D25:F0 (Integrated LAN Controller
MBARA)
4 KB anywhere in 4 GB range Integrated LAN Controller Enable using BAR in D25:F0 (Integrated LAN Controller
MBARB)
1 KB anywhere in 4 GB range USB EHCI Controller #1
1
Enable using standard PCI mechanism (D29:F0)
64 KB anywhere in 4 GB range USB xHCI Controller Enable using standard PCI mechanism (D20:F0)
FED0 X000h–FED0 X3FFh High Precision Event Timers
1
BIOS determines the “fixed” location which is one of four, 1-
KB ranges where X (in the first column) is 0h, 1h, 2h, or 3h.
FED4 0000h–FED4 FFFFh TPM on LPC None
Memory Base/Limit anywhere in 4
GB range
PCI Bridge Enable using standard PCI mechanism (D30:F0)
Prefetchable Memory Base/Limit
anywhere in 64-bit address range
PCI Bridge Enable using standard PCI mechanism (D30:F0)
64 KB anywhere in 4 GB range LPC LPC Generic Memory Range. Enable using setting bit[0] of
the LPC Generic Memory Range register (D31:F0:offset
98h).
32 Bytes anywhere in 64-bit
address range
SMBus Enable using standard PCI mechanism (D31:F3)
Table 4-4. Memory Decode Ranges from Processor Perspective (Sheet 2 of 3)
Memory Range Target Dependency/Comments