Datasheet

Register and Memory Mapping
Intel® Xeon® Processor D-1500 Product Family 187
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Notes:
1. All ranges are decoded directly from internal messages. The I/O cycles will not be seen on PCI, except the
range associated with PCI bridge.
2. The LAN range is typically not used, as the registers can also be accessed using a memory space.
3. There is also an alias 400h above the parallel port range that is used for ECP parallel ports.
4.4 Memory Map
Ta b l e 4- 4 shows (from the processor perspective) the memory ranges that Intel®
Xeon® Processor D-1500 Product Family decodes. Cycles that arrive from internal
messages that are not directed to any of the internal memory targets that decode
directly from internal messages will be driven out on PCI unless the Subtractive Decode
Policy bit is set (D31:F0:Offset 42h, bit 0).
PCI cycles generated by external PCI masters will be positively decoded unless they fall
in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for
PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller’s range, it will
be forwarded up to the processing unit. Software must not attempt locks to Intel®
Xeon® Processor D-1500 Product Family memory-mapped I/O ranges for EHCI and
HPET. If attempted, the lock is not honored which means potential deadlock conditions
may occur.
Parallel Port 3 Ranges in 64 KB I/O Space 8
3
LPC Peripheral
Serial Port 1 8 Ranges in 64 KB I/O Space 8 LPC Peripheral
Serial Port 2 8 Ranges in 64 KB I/O Space 8 LPC Peripheral
Floppy Disk Controller 2 Ranges in 64 KB I/O Space 8 LPC Peripheral
LAN Anywhere in 64 KB I/O Space 32
2
LAN Unit
LPC Generic 1 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral
LPC Generic 2 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral
LPC Generic 3 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral
LPC Generic 4 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral
I/O Trapping Ranges Anywhere in 64 KB I/O Space 1 to 256 Trap on Backbone
PCI Bridge Anywhere in 64 KB I/O Space I/O Base/
Limit
PCI Bridge
PCI Express* Root Ports Anywhere in 64 KB I/O Space I/O Base/
Limit
PCI Express Root Ports 1–8
KT Anywhere in 64 KB I/O Space 8 KT
Table 4-3. Variable I/O Decode Ranges (Sheet 2 of 2)
Range Name Mappable
Size
(Bytes)
Target
Table 4-4. Memory Decode Ranges from Processor Perspective (Sheet 1 of 3)
Memory Range Target Dependency/Comments
0000 0000h–000D FFFFh
0010 0000h–TOM
(Top of Memory)
Main Memory TOM registers in Host controller
000E 0000h–000E FFFFh LPC or SPI Bit 6 in BIOS Decode Enable register is set
000F 0000h–000F FFFFh LPC or SPI Bit 7 in BIOS Decode Enable register is set
FEC_ _000h–FEC_ _040h IO(x) APIC inside Intel®
Xeon® Processor D-1500
Product Family
_ _is controlled using APIC Range Select (ASEL) field and
APIC Enable (AEN) bit
FEC1 0000h–FEC1 7FFF PCI Express* Port 1 PCI Express* Root Port 1 I/OxAPIC Enable (PAE) set