Datasheet

Register and Memory Mapping
184 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
4.2 PCI Configuration Map
Each PCI function on Intel® Xeon® Processor D-1500 Product Family has a set of PCI
configuration registers. The register address map tables for these register sets are
included at the beginning of the chapter for the particular function.
Configuration Space registers are accessed through configuration cycles on the PCI bus
by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus
Specification, Revision 2.3.
Some of the PCI registers contain reserved bits. Software must deal correctly with
fields that are reserved. On reads, software must use appropriate masks to extract the
defined bits and not rely on reserved bits being any particular value. On writes,
software must ensure that the values of reserved bit positions are preserved. That is,
the values of reserved bit positions must first be read, merged with the new values for
other bit positions and then written back. The software does not need to perform read,
merge, write operation for the configuration address register.
In addition to reserved bits within a register, the configuration space contains reserved
locations. Software should not write to reserved PCI configuration locations in the
device-specific region (above address offset 3Fh).
4.3 I/O Map
The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be
moved, but in some cases can be disabled. Variable ranges can be moved and can also
be disabled.
4.3.1 Fixed I/O Address Ranges
Tab l e 4- 2 shows the Fixed I/O decode ranges from the processor perspective. For each
I/O range, there may be separate behavior for reads and writes. Internal message
cycles that go to target ranges that are marked as “Reserved” will not be decoded by
Intel® Xeon® Processor D-1500 Product Family, and will be passed to PCI, unless the
Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). If a PCI master targets
one of the fixed I/O target ranges, it will be positively decoded by Intel® Xeon®
Processor D-1500 Product Family in medium speed.
Address ranges that are not listed or marked “Reserved” are not decoded by Intel®
Xeon® Processor D-1500 Product Family (unless assigned to one of the variable
ranges).
Table 4-2. Fixed I/O Ranges Decoded by Intel® Xeon® Processor D-1500 Product Family
(Sheet 1 of 3)
I/O Address Read Target Write Target Internal Unit
00h–08h DMA Controller DMA Controller DMA
09h–0Eh RESERVED DMA Controller DMA
0Fh DMA Controller DMA Controller DMA
10h–18h DMA Controller DMA Controller DMA
19h–1Eh RESERVED DMA Controller DMA
1Fh DMA Controller DMA Controller DMA