Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 181
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
PCI Express defines a form of device hot reset which can be initiated through the
Bridge Control register of the root/switch port to which the device is attached.
However, the hot reset cannot be applied selectively to specific device functions. Also,
no similar standard functionality exists for resetting root-complex integrated devices.
Current reset limitations can be addressed through a function level reset (FLR)
mechanism that allows software to independently reset specific device functions.
3.25.4 Virtualization Support for Intel® Xeon® Processor D-1500
Product Family IOxAPIC
The Intel VT-d architecture extension requires Interrupt Messages to go through the
similar Address Remapping as any other memory requests. This is to allow domain
isolation for interrupts such that a device assigned in one domain is not allowed to
generate interrupts to another domain.
The Address Remapping for Intel VT-d is based on the Bus:Device:Function field
associated with the requests. Hence, it is required for the internal IOxAPIC to initiate
the Interrupt Messages using a unique Bus:Device:Function.
Intel® Xeon® Processor D-1500 Product Family supports BIOS programmable unique
Bus:Device:Function for the internal IOxAPIC. The Bus:Device:Function field does not
change the IOxAPIC functionality in anyway, nor promoting IOxAPIC as a stand-alone
device. The field is only used by the IOxAPIC in the following:
• As the Requestor ID when initiating Interrupt Messages to the processor
• As the Completer ID when responding to the reads targeting the IOxAPIC’s
Memory-Mapped I/O registers
3.25.5 Virtualization Support for High Precision Event Timer
(HPET)
The Intel VT-d architecture extension requires Interrupt Messages to go through the
similar Address Remapping as any other memory requests. This is to allow domain
isolation for interrupts such that a device assigned in one domain is not allowed to
generate interrupts to another domain.
The Address Remapping for Intel VT-d is based on the Bus:Device:Function field
associated with the requests. Hence, it is required for the HPET to initiate the direct
FSB Interrupt Messages using unique Bus:Device:Function.
Intel® Xeon® Processor D-1500 Product Family supports BIOS programmable unique
Bus:Device:Function for each of the HPET timers. The Bus:Device:Function field does
not change the HPET functionality in anyway, nor promoting it as a stand-alone device.
The field is only used by the HPET timer in the following:
• As the Requestor ID when initiating direct interrupt messages to the processor
• As the Completer ID when responding to the reads targeting its Memory-Mapped
registers
• The registers for the programmable Bus:Device:Function for HPET timer 7:0 reside
under the D31:F0 LPC Bridge’s configuration space.