Datasheet

18 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3-9 Flow for Port Enable / Device Present Bits ......................................................................... 125
3-10Serial Data transmitted over the SGPIO Interface .............................................................. 129
3-11EHCI with USB 2.0 with Rate Matching Hub....................................................................... 144
3-12Intel® Xeon® Processor D-1500 Product Family Intel
®
Management Engine (Intel
®
ME)
High-Level Block Diagram............................................................................................... 167
3-13Flash Descriptor Sections................................................................................................ 171
Tables
1-1 Industry Specifications .....................................................................................................24
1-2 Intel® Xeon® Processor D-1500 Product Family Integrated .................................................. 32
1-1 Intel® Xeon® Processor D-1500 Product Family Device and Revision ID ................................. 32
2-1 SoC Clock Inputs .............................................................................................................36
2-2 Clock Outputs ................................................................................................................. 36
2-3 Intel® Xeon® Processor D-1500 Product Family PLLs........................................................... 37
2-4 Modulator Blocks .............................................................................................................37
2-5 ICC Registers under Intel
®
Management Engine (Intel
®
ME) Control ...................................... 38
3-1 PCI Express* Ports 1 thru 4 - Supported Configurations........................................................ 50
3-2 PCI Express* Ports 5 thru 8 - Supported Configurations........................................................ 50
3-3 MSI versus PCI IRQ Actions .............................................................................................. 50
3-4 LAN Mode Support ........................................................................................................... 58
3-5 LPC Cycle Types Supported............................................................................................... 63
3-6 Start Field Bit Definitions ..................................................................................................64
3-7 Cycle Type Bit Definitions ................................................................................................. 64
3-8 Transfer Size Bit Definition................................................................................................64
3-9 SYNC Bit Definition ..........................................................................................................65
3-10DMA Transfer Size ...........................................................................................................69
3-11Address Shifting in 16-Bit I/O DMA Transfers ...................................................................... 69
3-12Counter Operating Modes ................................................................................................. 75
3-13Interrupt Controller Connections........................................................................................ 77
3-14Interrupt Status Registers.................................................................................................78
3-15Content of Interrupt Vector Byte........................................................................................ 78
3-16APIC Interrupt Mapping1 .................................................................................................. 84
3-17Stop Frame Explanation ................................................................................................... 87
3-18Data Frame Format.......................................................................................................... 87
3-19Configuration Bits Reset by RTCRST# Assertion ................................................................... 90
3-20General Power States for Systems Using Intel® Xeon® Processor D-1500 Product
Family............................................................................................................................ 92
3-21State Transition Rules for Intel® Xeon® Processor D-1500 Product Family.............................. 92
3-22System Power Plane......................................................................................................... 93
3-23Causes of SMI and SCI ..................................................................................................... 94
3-24Sleep Types .................................................................................................................... 97
3-25Causes of Wake Events .................................................................................................... 98
3-26GPI Wake Events.............................................................................................................99
3-27Transitions Due to Power Failure...................................................................................... 100
3-28Transitions Due to Power Button...................................................................................... 100
3-29Transitions Due to RI# Signal.......................................................................................... 101
3-30Write Only Registers with Read Paths in ALT Access Mode ................................................... 104
3-31PIC Reserved Bits Return Values...................................................................................... 105
3-32Register Write Accesses in ALT Access Mode...................................................................... 106
3-33SUSPWRDNACK / SUSWARN# / GPIO30 Pin Behavior ......................................................... 109
3-34SUSPWRDNACK during Reset .......................................................................................... 109
3-35Causes of Host and Global Resets .................................................................................... 111
3-36Event Transitions that Cause Messages............................................................................. 114
3-37Multi-activity LED Message Type ...................................................................................... 128
3-38Legacy Replacement Routing........................................................................................... 130
3-39Debug Port Behavior ...................................................................................................... 139
3-40I
2
C* Block Read ............................................................................................................ 149
3-41Enable for SMBALERT#................................................................................................... 151
3-42Enables for SMBus Slave Write and SMBus Host Events ...................................................... 152
3-43Enables for the Host Notify Command .............................................................................. 152
3-44Slave Write Registers ..................................................................................................... 153
3-45Command Types ........................................................................................................... 154
3-46Slave Read Cycle Format ................................................................................................ 155