Datasheet
Functional Description
Intel® Xeon® Processor D-1500 Product Family 179
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
• The 8-pin device is supported in either an 8-contact VDFPN (6x5 mm MLP) package
or an 8-contact WSON (5x6 mm) package. These packages can fit into a socket
that is land pattern compatible with the wide body SO8 package.
• The 8-pin device is supported in the SO8 (150 mil) and in the wide-body SO8
(200 mil) packages.
The 16-pin device is supported in the SO16 (300 mil) package.
3.23.9 PWM Outputs
This signal is driven as open-drain. An external pull-up resistor is integrated into the
fan to provide the rising edge of the PWM output signal. The PWM output is driven low
during reset, which represents 0% duty cycle to the fans. After reset de-assertion, the
PWM output will continue to be driven low until one of the following occurs:
• The internal PWM control register is programmed to a non-zero value by
appropriate firmware.
• The watchdog timer expires (enabled and set at 4 seconds by default).
• The polarity of the signal is inverted by firmware.
If a PWM output will be programmed to inverted polarity for a particular fan, then the
low voltage driven during reset represents 100% duty cycle to the fan.
3.23.10 TACH Inputs
This signal is driven as an open-collector or open-drain output from the fan. An
external pull-up is expected to be implemented on the motherboard to provide the
rising edge of the TACH input. This signal has analog hysteresis and digital filtering due
to the potentially slow rise and fall times. This signal has a weak internal pull-up
resistor to keep the input buffer from floating if the TACH input is not connected to a
fan.
3.24 Feature Capability Mechanism
A set of registers is included in Intel® Xeon® Processor D-1500 Product Family LPC
Interface (Device 31, Function 0, offset E0h–EBh) that allows the system software or
BIOS to easily determine the features supported by Intel® Xeon® Processor D-1500
Product Family. These registers can be accessed through LPC PCI configuration space,
thus allowing for convenient single point access mechanism for chipset feature
detection.
This set of registers consists of:
• Capability ID (FDCAP)
• Capability Length (FDLEN)
• Capability Version and Vendor-Specific Capability ID (FDVER)
• Feature Vector (FVECT)