Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 177
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Both mechanisms are logically OR’d together such that if any of the mechanisms
indicate that the access should be blocked, then it is blocked. Ta b l e 3- 5 4 provides a
summary of the mechanisms.
A blocked command will appear to software to finish, except that the Blocked Access
status bit is set in this case.
3.23.5.2 BIOS Range Write Protection
Intel® Xeon® Processor D-1500 Product Family provides a method for blocking writes
to specific ranges in the SPI flash when the Protected BIOS Ranges are enabled. This is
achieved by checking the Opcode type information (which can be locked down by the
initial Boot BIOS) and the address of the requested command against the base and
limit fields of a Write Protected BIOS range.
Note: Once BIOS has locked down the Protected BIOS Range registers, this mechanism
remains in place until the next system reset.
3.23.5.3 SMI# Based Global Write Protection
Intel® Xeon® Processor D-1500 Product Family provides a method for blocking writes
to the SPI flash when the Write Protected bit is cleared (that is, protected). This is
achieved by checking the Opcode type information (which can be locked down by the
initial Boot BIOS) of the requested command.
The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as
they do for the FWH BIOS.
3.23.6 Flash Device Configurations
Intel® Xeon® Processor D-1500 Product Family-based platform must have a SPI flash
connected directly to Intel® Xeon® Processor D-1500 Product Family with a valid
descriptor and Intel Management Engine Firmware. BIOS may be stored in other
locations such as Firmware Hub and SPI flash hooked up directly to an embedded
controller. Note this will not avoid the direct SPI flash connected to Intel® Xeon®
Processor D-1500 Product Family requirement.
3.23.7 SPI Flash Device Recommended Pinout
Ta b l e 3- 5 5 contains the recommended serial flash device pin-out for an 8-pin device.
Use of the recommended pin-out on an 8-pin device reduces complexities involved with
designing the serial flash device onto a motherboard and allows for support of a
common footprint usage model (refer to Section 3.23.8.1).
Table 3-54. Flash Protection Mechanism Summary
Mechanism
Accesses
Blocked
Range
Specific?
Reset-Override
or SMI#-
Override?
Equivalent Function on FWH
BIOS Range
Write Protection
Writes Yes Reset Override FWH Sector Protection
Write Protect Writes No SMI# Override Same as Write Protect in Intel
®
ICHs for FWH