Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 175
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
• Flash part must be uniform 4-KB erasable block throughout the entire device or
have 64 KB blocks with the first block (lowest address) divided into 4-KB or 8-KB
blocks.
• Write protection scheme must meet SPI flash unlocking requirements for Intel ME.
3.23.4.3.1 SPI Flash Unlocking Requirements for Intel
®
Management Engine (Intel
®
ME)
Flash devices must be globally unlocked (read, write and erase access on the ME
region) from power on by writing 00h to the flash’s status register to disable write
protection.
If the status register must be unprotected, it must use the enable write status register
command 50h or write enable 06h.
Opcode 01h (write to status register) must then be used to write a single byte of 00h
into the status register. This must unlock the entire part. If the SPI flash’s status
register has non-volatile bits that must be written to, bits [5:2] of the flash’s status
register must be all 0h to indicate that the flash is unlocked.
If bits [5:2] return a non zero values, the Intel ME firmware will send a write of 00h to
the status register. This must keep the flash part unlocked.
If there is no need to execute a write enable on the status register, then opcodes 06h
and 50h must be ignored.
After global unlock, BIOS has the ability to lock down small sections of the flash as long
as they do not involve the Intel ME or GbE region.
3.23.4.4 Hardware Sequencing Requirements
Ta b l e 3- 5 3 contains a list of commands and the associated opcodes that a SPI-based
serial flash device must support in order to be compatible with hardware sequencing.
Table 3-53. Hardware Sequencing Commands and Opcode Requirements
Commands Opcode Notes
Write to Status Register 01h Writes a byte to SPI flash’s status register. Enable Write to Status
Register command must be run prior to this command.
Program Data 02h Single byte or 64 byte write as determined by flash part
capabilities and software.
Read Data 03h
Write Disable 04h
Read Status 05h Outputs contents of SPI flash’s status register
Write Enable 06h
Fast Read 0Bh
Enable Write to Status
Register
50h or 60h Enables a bit in the status register to allow an update to the
status register
Erase Programm
able
256B, 4 Kbyte, 8 Kbyte or 64 Kbyte
Full Chip Erase C7h
JEDEC ID 9Fh See Section 3.23.4.4.3.