Datasheet

Functional Description
170 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Only three masters can access the four regions: Host processor running BIOS code,
Integrated Gigabit Ethernet and Host processor running Gigabit Ethernet Software, and
Intel Management Engine. The Flash Descriptor is in Region 0 and it must be located in
the first sector of Device 0 (Offset 0).
Flash Region Sizes
SPI flash space requirements differ by platform and configuration. The Flash Descriptor
requires one 4 KB or larger block. GbE requires two 4 KB or larger blocks. The amount
of flash space consumed is dependent on the erase granularity of the flash part and the
platform requirements for the Intel ME and BIOS regions.
3.23.2 Flash Descriptor
The maximum size of the Flash Descriptor is 4 KB. If the block/sector size of the SPI
flash device is greater than 4 KB, the flash descriptor will only use the first 4 KB of the
first block. The flash descriptor requires its own block at the bottom of memory (00h).
The information stored in the Flash Descriptor can only be written during the
manufacturing process as its read/write permissions must be set to Read only when the
computer leaves the manufacturing floor.
The Flash Descriptor is made up of eleven sections (see Figure 3-13).
Table 3-51. Region Size versus Erase Granularity of Flash Components
Region
Size with 4 KB
Blocks
Size with 8 KB Blocks Size with 64 KB Blocks
Descriptor 4 KB 8 KB 64 KB
GbE 8 KB 16 KB 128 KB
BIOS Varies by Platform Varies by Platform Varies by Platform
Intel ME Varies by Platform Varies by Platform Varies by Platform