Datasheet

Intel® Xeon® Processor D-1500 Product Family 17
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
16.1.6 PI— Programming Interface Register .............................................................547
16.1.7 SCC—Sub Class Code Register ......................................................................547
16.1.8 BCC—Base Class Code Register.....................................................................547
16.1.9 CLS—Cache Line Size Register ......................................................................547
16.1.10 LT—Latency Timer Register ..........................................................................548
16.1.11 HTYPE—Header Type Register.......................................................................548
16.1.12 TBAR—Thermal Base Register .......................................................................548
16.1.13 TBARH—Thermal Base High DWord Register ...................................................548
16.1.14 SVID—Subsystem Vendor ID Register ............................................................549
16.1.15 SID—Subsystem ID Register.........................................................................549
16.1.16 CAP_PTR—Capabilities Pointer Register ..........................................................549
16.1.17 INTLN—Interrupt Line Register......................................................................549
16.1.18 INTPN—Interrupt Pin Register .......................................................................550
16.1.19 TBARB—BIOS Assigned Thermal Base Address Register....................................550
16.1.20 TBARBH—BIOS Assigned Thermal Base High
DWord Register...........................................................................................550
16.1.21 PID—PCI Power Management Capability ID Register.........................................550
16.1.22 PC—Power Management Capabilities Register..................................................551
16.1.23 PCS—Power Management Control And Status Register .....................................551
16.2 Thermal Memory Mapped Configuration Registers (Thermal Sensor – D31:F26)............... 551
16.2.1 TEMP—Temperature Register ........................................................................552
16.2.2 TSC—Thermal Sensor Control Register ...........................................................552
16.2.3 TSS—Thermal Sensor Status Register ............................................................553
16.2.4 TSEL — Thermal Sensor Enable and Lock Register ...........................................553
16.2.5 TSREL—Thermal Sensor Reporting Enable and Lock Register.............................553
16.2.6 TSMIC—Thermal Sensor SMI Control Register .................................................554
16.2.7 CTT—Catastrophic Trip Point Register ............................................................554
16.2.8 TAHV—Thermal Alert High Value Register .......................................................554
16.2.9 TALV—Thermal Alert Low Value Register ........................................................554
16.2.10 TL—Throttle Levels Register..........................................................................554
16.2.11 PHL—Intel® Xeon® Processor D-1500 Product Family Hot Level Register ...........555
16.2.12 PHLC—PHL Control Register..........................................................................555
16.2.13 TAS — Thermal Alert Status Register .............................................................555
16.2.14 TSPIEN — PCI Interrupt Event Enables Register ..............................................556
16.2.15 TSGPEN—General Purpose Event Enables Register ...........................................556
17 Intel® Management Engine Subsystem Registers (D22:F[3:0]).....................................557
17.1 First Intel
®
Management Engine Interface (Intel
®
MEI) Configuration Registers
(Intel
®
MEI 1 — D22:F0) .........................................................................................557
17.1.1 PCI Configuration Registers (Intel
®
MEI 1—D22:F0) ........................................557
17.1.2 MEI0_MBAR—Intel
®
MEI 1 MMIO Registers.....................................................567
17.2 Second Intel
®
Management Engine Interface (Intel
®
MEI 2) Configuration Registers
(Intel
®
MEI 2—D22:F1) ...........................................................................................569
17.2.1 PCI Configuration Registers (Intel
®
MEI 2—D22:F2) ........................................569
17.2.2 MEI1_MBAR—Intel
®
MEI 2 MMIO Registers.....................................................576
17.3 IDE Redirect IDER Registers (IDER — D22:F2)............................................................578
17.3.1 PCI Configuration Registers (IDER—D22:F2) ...................................................578
17.3.2 IDER BAR0 Registers ...................................................................................585
17.3.3 IDER BAR1 Registers ...................................................................................592
17.3.4 IDER BAR4 Registers ...................................................................................593
17.4 Serial Port for Remote Keyboard and Text (KT) Redirection (KT — D22:F3).....................598
17.4.1 PCI Configuration Registers (KT — D22:F3) ....................................................598
17.4.2 KT IO/Memory Mapped Device Registers ........................................................603
Figures
3-1 Generation of SERR# to Platform .......................................................................................53
3-2 LPC Interface Diagram......................................................................................................63
3-3 Intel® Xeon® Processor D-1500 Product Family DMA Controller ............................................67
3-4 DMA Request Assertion through LDRQ# ..............................................................................71
3-5 Conceptual Diagram of SLP_LAN#....................................................................................108
3-6 TCO Legacy/Compatible Mode SMBus Configuration ............................................................114
3-7 Advanced TCO Mode.......................................................................................................115
3-8 Serial Post over GPIO Reference Circuit.............................................................................117