Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 169
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Intel® Xeon® Processor D-1500 Product Family adds third chip select SPI_CS2# for
TPM support over SPI. TPM Bus will use SPI_CLK, SPI_MISO, SPI_MOSI and SPI_CS2#
SPI signals.
Note: Communication on the SPI bus is done with a Master – Slave protocol. The Slave is
connected to Intel® Xeon® Processor D-1500 Product Family and is implemented as a
tri-state bus.If Boot BIOS Strap =’00’ then LPC is selected as the location for BIOS.
BIOS may still be placed on LPC, but all platforms with Intel® Xeon® Processor D-1500
Product Family require a SPI flash connected directly to Intel® Xeon® Processor D-
1500 Product Family's SPI bus with a valid descriptor connected to Chip Select 0 in
order to boot.
Note: When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected
by Intel® Xeon® Processor D-1500 Product Family, LPC based BIOS flash is disabled.
3.23.1 SPI Supported Feature Overview
SPI Flash on Intel® Xeon® Processor D-1500 Product Family has two operational
modes, descriptor and non-descriptor.
3.23.1.1 Non-Descriptor Mode
Non-Descriptor Mode is not supported as a valid flash descriptor is required for all
Intel® Xeon® Processor D-1500 Product Family Platforms.
3.23.1.2 Descriptor Mode
Descriptor Mode is required. It enables many features of the chipset:
• Integrated Gigabit Ethernet and Host processor for Gigabit Ethernet Software
• Intel Management Engine Firmware
• PCI Express* root port configuration
• Supports up to two SPI components using two separate chip select pins
• Hardware enforced security restricting master accesses to different regions
• Chipset Soft Strap regions provides the ability to use Flash NVM as an alternative to
hardware pull-up/pull-down resistors for Intel® Xeon® Processor D-1500 Product
Family and processor
• Supports the SPI Fast Read instruction and frequencies of up to 50 MHz
• Support Single Input, Dual Output Fast read
• Uses standardized Flash Instruction Set
3.23.1.2.1 SPI Flash Regions
In Descriptor Mode the Flash is divided into five separate regions:
Region Content
0 Flash Descriptor
1BIOS
2 Intel Management Engine
3 Gigabit Ethernet
4Platform Data