Datasheet

Functional Description
168 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
• The SPI flash device stores Intel ME Firmware code that is executed by the Intel ME
for its operations. Intel® Xeon® Processor D-1500 Product Family controls the
flash device through the SPI interface and internal logic.
• In the M0 power state, the Intel ME FW code is loaded from SPI flash into DRAM
and cached in secure and isolated SRAM. In order to interface with DRAM, the Intel
ME utilizes the integrated memory controller (IMC). Communication between the
IMC and the intel ME occurs in only M0 power state. In the lower Intel ME power
state, M3, code is executed exclusively from secure and isolated Intel ME local
RAM.
• The LAN controller embedded in Intel® Xeon® Processor D-1500 Product Family as
well as the Intel Gigabit Platform LAN Connect device are required for Intel ME.
• BIOS provides asset detection and POST diagnostics.
3.23 Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a lower-cost
alternative for system flash versus the Firmware Hub on the LPC bus.
The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In
(MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select
(SPI_CS[1:0]#). SPI also adds 2 extra pins SPI_IO2 and SPI_IO3 for Quad I/O
operation.
Intel® Xeon® Processor D-1500 Product Family supports up to two SPI flash devices
using two separate Chip Select pins. Each SPI flash device can be up to 16 MB. Intel®
Xeon® Processor D-1500 Product Family SPI interface supports 20 MHz, 33 MHz, and
50 MHz SPI devices. A SPI Flash device on with Chip Select 0 with a valid descriptor
MUST be attached directly to Intel® Xeon® Processor D-1500 Product Family.
Note: When operating at 50 MHz, because of the 40% duty cycle Intel® Xeon® Processor D-
1500 Product Family must use by dividing down from a 125 MHz clock, Intel® Xeon®
Processor D-1500 Product Family SPI Flash Controller cannot meet the minimum high
timing requirements of a 50 MHz SPI Flash component and a 66 MHz rated or faster SPI
Flash component must be used.
Intel® Xeon® Processor D-1500 Product Family supports fast read which consist of:
1. Dual Output Fast Read (Single Input Dual Output)
2. Dual I/O Fast Read (Dual Input Dual Output)
3. Quad Output Fast Read (Single Input Quad Output)
4. Quad I/O Fast Read (Quad Input Quad Output)
Fast Read function will be enabled if the particular SPI part supports one of the function
mentioned above along with support for SFDP (Serial Flash Discoverable Parameter).
Intel® Xeon® Processor D-1500 Product Family adds support for SFDP. SFDP is a
JEDEC* standard that provides consistent method for describing functional and feature
capabilities of serial flash devices in a standard set of internal parameter table. Intel®
Xeon® Processor D-1500 Product Family SPI controller reads the internal parameter
table and enables divergent features of multiple SPI vendor parts.