Datasheet
Functional Description
166 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
5. When Intel® Xeon® Processor D-1500 Product Family updates the Block Read data
structure, the external controller gets a NACK during this period.
a. To ensure atomicity of the SMBus data read with respect to the data itself, when
the data buffer is being updated, Intel® Xeon® Processor D-1500 Product
Family will NACK the Block Read transaction.
b. The update is only a few micro-seconds, so very short in terms of SMBus polling
time; therefore, the next read should be successful. The external controller
should attempt 3 reads to handle this condition before moving on.
c. If the Block read has started (that is, the address is ACK'ed) then the entire read
will complete successfully, and Intel® Xeon® Processor D-1500 Product Family
will update the data only after the SMBus read has completed.
6. System is going from S0 to S4/S5. The thermal monitoring FW is fully operational if
the system is in S0/S1, so the following only applies to S4/S5.
a. When Intel® Xeon® Processor D-1500 Product Family detects the OS request
to go to S4/S5, it will take the SMLink0 controller offline as part of the system
preparation. The external controller will see a period where its transactions are
getting NACK'ed, and then see SLP_S3# assert.
This period is relatively short (a couple of seconds depending on how long all the
devices take to place themselves into the D3 state), and would be far less than
the 30 second limit mentioned above.
7. TEMP_ALERT# – Since there can be an internal reset, the TEMP_ALERT# may get
asserted after the reset. The external controller must accept this assertion and
handle it.
3.21.3.8.1 Example Algorithm for Handling Transaction
One algorithm for the transaction handling could be summarized as follows. This is just
an example to illustrate the above rules. There could be other algorithms that can
achieve the same results.
1. Perform SMBus transaction.
2. If ACK, then continue
3. If NACK
a. Try again for 2 more times, in case Intel® Xeon® Processor D-1500 Product
Family is busy updating data.
b. If 3 successive transactions receive NACK, then
- Ramp fans, assuming some general long reset or failure
- Try every 1-10 seconds to see if SMBus transactions are now working
- f they start then return to step 1
- If they continue to fail, then stay in this step and poll, but keep the fans
ramped up or implement some other failure recovery mechanism.
3.22 Intel
®
Management Engine (Intel
®
ME) and Intel
®
Management Engine Firmware (Intel
®
ME FW) 9.0
Key properties of Intel Management Engine (Intel ME):
• Connectivity