Datasheet

16 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
15.1.22 OPMENU—Opcode Menu Configuration Register (SPI Memory Mapped
Configuration Registers) .............................................................................. 530
15.1.23 BBAR—BIOS Base Address Configuration Register (SPI Memory Mapped
Configuration Registers) .............................................................................. 531
15.1.24 FDOC—Flash Descriptor Observability Control Register (SPI Memory Mapped
Configuration Registers) .............................................................................. 531
15.1.25 FDOD—Flash Descriptor Observability Data Register (SPI Memory Mapped
Configuration Registers) .............................................................................. 532
15.1.26 AFC—Additional Flash Control Register (SPI Memory Mapped Configuration
Registers).................................................................................................. 532
15.1.27 LVSCC— Host Lower Vendor Specific Component Capabilities Register (SPI
Memory Mapped Configuration Registers)....................................................... 532
15.1.28 UVSCC— Host Upper Vendor Specific Component Capabilities Register (SPI
Memory Mapped Configuration Registers)....................................................... 533
15.1.29 FPB—Flash Partition Boundary Register (SPI Memory Mapped Configuration
Registers).................................................................................................. 534
15.1.30 SRDL—Soft Reset Data Lock Register (SPI Memory Mapped Configuration
Registers).................................................................................................. 535
15.1.31 SRDC—Soft Reset Data Control Register (SPI Memory Mapped
Configuration Registers) .............................................................................. 535
15.1.32 SRD—Soft Reset Data Register (SPI Memory Mapped Configuration
Registers).................................................................................................. 535
15.2 Flash Descriptor Records ......................................................................................... 535
15.3 OEM Section .......................................................................................................... 535
15.4 GbE SPI Flash Program Registers.............................................................................. 536
15.4.1 GLFPR –Gigabit LAN Flash Primary Region Register (GbE LAN Memory
Mapped Configuration Registers)................................................................... 537
15.4.2 HSFS—Hardware Sequencing Flash Status Register (GbE LAN Memory
Mapped Configuration Registers)................................................................... 537
15.4.3 HSFC—Hardware Sequencing Flash Control Register (GbE LAN Memory
Mapped Configuration Registers)................................................................... 538
15.4.4 FADDR—Flash Address Register (GbE LAN Memory Mapped Configuration
Registers).................................................................................................. 538
15.4.5 FDATA0—Flash Data 0 Register (GbE LAN Memory Mapped Configuration
Registers).................................................................................................. 539
15.4.6 FRAP—Flash Regions Access Permissions Register (GbE LAN Memory
Mapped Configuration Registers)................................................................... 539
15.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register (GbE LAN Memory
Mapped Configuration Registers)................................................................... 540
15.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register (GbE LAN Memory
Mapped Configuration Registers)................................................................... 540
15.4.9 FREG2—Flash Region 2 (Intel
®
ME) Register (GbE LAN Memory Mapped
Configuration Registers) .............................................................................. 540
15.4.10 FREG3—Flash Region 3 (GbE) Register (GbE LAN Memory Mapped
Configuration Registers) .............................................................................. 540
15.4.11 PR0—Protected Range 0 Register (GbE LAN Memory Mapped Configuration
Registers).................................................................................................. 541
15.4.12 PR1—Protected Range 1 Register (GbE LAN Memory Mapped Configuration
Registers).................................................................................................. 541
15.4.13 SSFS—Software Sequencing Flash Status Register (GbE LAN Memory
Mapped Configuration Registers)................................................................... 542
15.4.14 SSFC—Software Sequencing Flash Control Register (GbE LAN Memory
Mapped Configuration Registers)................................................................... 542
15.4.15 PREOP—Prefix Opcode Configuration Register (GbE LAN Memory Mapped
Configuration Registers) .............................................................................. 543
15.4.16 OPTYPE—Opcode Type Configuration Register (GbE LAN Memory Mapped
Configuration Registers) .............................................................................. 543
15.4.17 OPMENU—Opcode Menu Configuration Register (GbE LAN Memory Mapped
Configuration Registers) .............................................................................. 544
16 Thermal Sensor Registers (D31:F6)...............................................................................545
16.1 PCI Bus Configuration Registers ............................................................................... 545
16.1.1 VID—Vendor Identification Register............................................................... 545
16.1.2 DID—Device Identification Register ............................................................... 546
16.1.3 CMD—Command Register ............................................................................ 546
16.1.4 STS—Status Register .................................................................................. 546
16.1.5 RID—Revision Identification Register ............................................................. 547