Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 157
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
is illegal for SMBus Read or Write protocol), and the address matches Intel® Xeon®
Processor D-1500 Product Family’s Slave Address, Intel® Xeon® Processor D-1500
Product Family will still grab the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–
Read sequence beginning at Bit 20. Once again, if the Address matches Intel® Xeon®
Processor D-1500 Product Family’s Receive Slave Address, it will assume that the
protocol is followed, ignore bit 28, and proceed with the Slave Read cycle.
Note: An external microcontroller must not attempt to access Intel® Xeon® Processor D-
1500 Product Family’s SMBus Slave logic until at least 1 second after both RTCRST#
and RSMRST# are de-asserted (high).
3.20.7.3 Slave Read of RTC Time Bytes
Intel® Xeon® Processor D-1500 Product Family SMBus slave interface allows external
SMBus master to read the internal RTC’s time byte registers.
The RTC time bytes are internally latched by Intel® Xeon® Processor D-1500 Product
Family’s hardware whenever RTC time is not changing and SMBus is idle. This ensures
that the time byte delivered to the slave read is always valid and it does not change
when the read is still in progress on the bus. The RTC time will change whenever
hardware update is in progress, or there is a software write to the RTC time bytes.
Intel® Xeon® Processor D-1500 Product Family SMBus slave interface only supports
Byte Read operation. The external SMBus master will read the RTC time bytes one after
another. It is software’s responsibility to check and manage the possible time rollover
when subsequent time bytes are read.
For example, assuming the RTC time is 11 hours: 59 minutes: 59 seconds. When the
external SMBus master reads the hour as 11, then proceeds to read the minute, it is
possible that the rollover happens between the reads and the minute is read as 0. This
results in 11 hours: 0 minute instead of the correct time of 12 hours: 0 minutes. Unless
it is certain that rollover will not occur, software is required to detect the possible time
rollover by reading multiple times such that the read time bytes can be adjusted
accordingly
if needed.
3.20.7.4 Format of Host Notify Command
Intel® Xeon® Processor D-1500 Product Family tracks and responds to the standard
Host Notify command as specified in the System Management Bus (SMBus)
Specification, Version 2.0. The host address for this command is fixed to 0001000b. If
Intel® Xeon® Processor D-1500 Product Family already has data for a previously-
received host notify command which has not been serviced yet by the host software (as
indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address
byte of the protocol. This allows the host to communicate non-acceptance to the
master and retain the host notify address and data values for the previous cycle until
host software completely services the interrupt.
Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any
necessary reads of the address and data registers.
Ta b l e 3- 4 8 shows the Host Notify format.