Datasheet

Functional Description
156 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.20.7.2.1 Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit –
Address– Write bit sequence. When Intel® Xeon® Processor D-1500 Product Family
detects that the address matches the value in the Receive Slave Address register, it will
assume that the protocol is always followed and ignore the Write bit (Bit 9) and signal
an Acknowledge during bit 10. In other words, if a Start –Address–Read occurs (which
401 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system
cover has probably been opened.
11 = BTI Temperature Event occurred. This bit will be set if Intel® Xeon®
Processor D-1500 Product Family THRM# input signal is active. Else this bit will read
“0.”
2 DOA Processor Status. This bit will be 1 to indicate that the processor is dead
31 = SECOND_TO_STS bit set. This bit will be set after the second time-out
(SECOND_TO_STS bit) of the Watchdog Timer occurs.
6:4 Reserved. Will always be 0, but software should ignore.
7 Reflects the value of the GPIO[11]/SMBALERT# pin (and is dependent upon the
value of the GPI_INV[11] bit. If the GPI_INV[11] bit is 1, then the value in this bit
equals the level of the GPI[11]/SMBALERT# pin
(high = 1, low = 0).
If the GPI_INV[11] bit is 0, then the value of this bit will equal the inverse of the
level of the GPIO[11]/SMBALERT# pin (high = 0, low = 1).
5 0 FWH bad bit. This bit will be 1 to indicate that the FWH read returned FFh, which
indicates that it is probably blank.
1Reserved
2 SYS_PWROK Failure Status: This bit will be 1 if the SYSPWR_FLR bit in the
GEN_PMCON_2 register is set.
3 Reserved
4 Reserved
5 POWER_OK_BAD: Indicates the failure core power well ramp during boot/resume.
This bit will be active if the SLP_S3# pin is de-asserted and PCH_PWROK pin is not
asserted.
6 Thermal Trip: This bit will shadow the state of processor Thermal Trip status bit
(CTS) (16.2.1.2, GEN_PMCON_2, bit 3). Events on signal will not create a event
message
7 Reserved: Default value is “X”
Note: Software should not expect a consistent value when this bit is read through
SMBUS/SMLink
6 7:0 Contents of the Message 1 register. Refer to Section 7.9.8 for the description of this
register.
7 7:0 Contents of the Message 2 register. Refer to Section 7.9.8 for the description of this
register.
8 7:0 Contents of the TCO_WDCNT register. Refer to Section 7.9.9 for the description of
this register.
9 7:0 Seconds of the RTC
A 7:0 Minutes of the RTC
B7:0Hours of the RTC
C 7:0 “Day of Week” of the RTC
D 7:0 “Day of Month” of the RTC
E 7:0 Month of the RTC
F7:0Year of the RTC
10h–FFh 7:0 Reserved
Table 3-47. Data Values for Slave Read Registers (Sheet 2 of 2)
Register Bits Description