Datasheet

Functional Description
154 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: The external microcontroller is responsible to make sure that it does not update the contents of the data
byte registers until they have been read by the system processor. Intel® Xeon® Processor D-1500
Product Family overwrites the old value with any new value received. A race condition is possible where
the new value is being written to the register just at the time it is being read. Intel® Xeon® Processor
D-1500 Product Family will not attempt to cover this race condition (that is, unpredictable results in this
case).
3.20.7.2 Format of Read Command
The external master performs Byte Read commands to Intel® Xeon® Processor D-
1500 Product Family SMBus Slave interface. The “Command” field (bits 18:11) indicate
which register is being accessed. The Data field (bits 30:37) contain the value that
should be read from that register.
6–7 Reserved
8 Reserved
9–FFh Reserved
Table 3-44. Slave Write Registers (Sheet 2 of 2)
Register Function
Table 3-45. Command Types
Command Type Description
0 Reserved
1 WAKE/SMI#. This command wakes the system if it is not already awake. If system is
already awake, an SMI# is generated.
Note: The SMB_WAK_STS bit will be set by this command, even if the system is already
awake. The SMI handler should then clear this bit.
2 Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and has the
same effect as the Powerbutton Override occurring.
3 HARD RESET WITHOUT CYCLING: This command causes a hard reset of the system
(does not include cycling of the power supply). This is equivalent to a write to the CF9h
register with Bits 2:1 set to 1, but Bit 3 clear to 0.
4 HARD RESET SYSTEM. This command causes a hard reset of the system (including
cycling of the power supply). This is equivalent to a write to the CF9h register with Bits
3:1 set to 1.
5 Disable the TCO Messages. This command will disable Intel® Xeon® Processor D-1500
Product Family from sending Heartbeat and Event messages (as described in
Section 3.13). Once this command has been executed, Heartbeat and Event message
reporting can only be re-enabled by assertion and de-assertion of the RSMRST# signal.
6 WD RELOAD: Reload watchdog timer.
7 Reserved
8 SMLINK_SLV_SMI. When Intel® Xeon® Processor D-1500 Product Family detects this
command type while in the S0 state, it sets the SMLINK_SLV_SMI_STS bit (see
Section 7.9.5). This command should only be used if the system is in an S0 state. If the
message is received during S1–S5 states, Intel® Xeon® Processor D-1500 Product Family
acknowledges it, but the SMLINK_SLV_SMI_STS bit does not get set.
Note: It is possible that the system transitions out of the S0 state at the same time that
the SMLINK_SLV_SMI command is received. In this case, the
SMLINK_SLV_SMI_STS bit may get set but not serviced before the system goes
to sleep. Once the system returns to S0, the SMI associated with this bit would
then be generated. Software must be able to handle this scenario.
9–FFh Reserved.