Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 153
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Intel® Xeon® Processor D-1500 Product Family to decode cycles, and allows an
external microcontroller to perform specific actions. Key features and capabilities
include:
• Supports decode of three types of messages: Byte Write, Byte Read, and Host
Notify.
• Receive Slave Address register: This is the address that Intel® Xeon® Processor D-
1500 Product Family decodes. A default value is provided so that the slave interface
can be used without the processor having to program this register.
• Receive Slave Data register in the SMBus I/O space that includes the data written
by the external microcontroller.
• Registers that the external microcontroller can read to get the state of Intel®
Xeon® Processor D-1500 Product Family.
• Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due
to the reception of a message that matched the slave address.
— Bit 0 of the Slave Status Register for the Host Notify command
— Bit 16 of the SMI Status Register (Section 7.8.3.8) for all others
Note: The external microcontroller should not attempt to access Intel® Xeon® Processor D-
1500 Product Family SMBus slave logic until either:
— 800 milliseconds after both: RTCRST# is high and RSMRST# is high, OR
—The PLTRST# de-asserts
If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more
in the middle of a cycle, Intel® Xeon® Processor D-1500 Product Family slave logic's
behavior is undefined. This is interpreted as an unexpected idle and should be avoided
when performing management activities to the slave logic.
Note: When an external microcontroller accesses the SMBus Slave Interface over the SMBus
a translation in the address is needed to accommodate the least significant bit used for
read/write control. For example, if Intel® Xeon® Processor D-1500 Product Family
slave address (RCV_SLVA) is left at 44h (default), the external micro controller would
use an address of 88h/89h (write/read).
3.20.7.1 Format of Slave Write Cycle
The external master performs Byte Write commands to Intel® Xeon® Processor D-
1500 Product Family SMBus Slave I/F. The “Command” field (bits 11:18) indicate which
register is being accessed. The Data field (bits 20:27) indicate the value that should be
written to that register.
Ta b l e 3- 4 4 has the values associated with the registers.
Table 3-44. Slave Write Registers (Sheet 1 of 2)
Register Function
0 Command Register. See Ta b l e 3 - 4 5 for legal values written to this register.
1–3 Reserved
4 Data Message Byte 0
5 Data Message Byte 1