Datasheet
Functional Description
152 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.20.5 SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enable and the signal is asserted,
Intel® Xeon® Processor D-1500 Product Family can generate an interrupt, an SMI#, or
a wake event from S1–S5.
3.20.6 SMBus CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, Intel® Xeon® Processor D-1500
Product Family automatically calculates and drives CRC at the end of the transmitted
packet for write cycles, and will check the CRC for read cycles. It will not transmit the
contents of the PEC register for CRC. The PEC bit must not be set in the Host Control
register if this bit is set, or unspecified behavior will result.
If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the
Auxiliary Status register at Offset 0Ch will be set.
3.20.7 SMBus Slave Interface
Intel® Xeon® Processor D-1500 Product Family SMBus Slave interface is accessed
using the SMBus. The SMBus slave logic will not generate or handle receiving the PEC
byte and will only act as a Legacy Alerting Protocol device. The slave interface allows
Table 3-42. Enables for SMBus Slave Write and SMBus Host Events
Event
INTREN (Host Control
I/O Register, Offset
02h, Bit 0)
SMB_SMI_EN (Host
Configuration Register,
D31:F3:Offset 40h,
Bit 1)
Event
Slave Write to Wake/SMI#
Command
X X Wake generated when asleep.
Slave SMI# generated when awake
(SMBUS_SMI_STS).
Slave Write to
SMLINK_SLAVE_SMI
Command
X X Slave SMI# generated when in the
S0 state (SMBUS_SMI_STS)
Any combination of Host
Status Register [4:1]
asserted
0XNone
1 0 Interrupt generated
11Host SMI# generated
Table 3-43. Enables for the Host Notify Command
HOST_NOTIFY_INTREN
(Slave Control I/O
Register, Offset 11h, Bit
0)
SMB_SMI_EN (Host
Config Register,
D31:F3:Off40h,
Bit 1)
HOST_NOTIFY_WKEN
(Slave Control I/O
Register, Offset 11h, Bit
1)
Result
0X0None
XX 1Wake generated
10XInterrupt generated
1 1 X Slave SMI# generated
(SMBUS_SMI_STS)