Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 151
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.20.3 Bus Timing
3.20.3.1 Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that Intel®
Xeon® Processor D-1500 Product Family as an SMBus master would like. They have
the capability of stretching the low time of the clock. When Intel® Xeon® Processor D-
1500 Product Family attempts to release the clock (allowing the clock to go high), the
clock will remain low for an extended period of time.
Intel® Xeon® Processor D-1500 Product Family monitors the SMBus clock line after it
releases the bus to determine whether to enable the counter for the high time of the
clock. While the bus is still low, the high time counter must not be enabled. Similarly,
the low period of the clock can be stretched by an SMBus master if it is not ready to
send or receive data.
3.20.3.2 Bus Time Out (Intel® Xeon® Processor D-1500 Product Family as
SMBus Master)
If there is an error in the transaction, such that an SMBus device does not signal an
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
will time out. Intel® Xeon® Processor D-1500 Product Family will discard the cycle and
set the DEV_ERR bit. The time out minimum is 25 ms (800 RTC clocks). The time-out
counter inside Intel® Xeon® Processor D-1500 Product Family will start after the last
bit of data is transferred by Intel® Xeon® Processor D-1500 Product Family and it is
waiting for a response.
The 25-ms time-out counter will not count under the following conditions:
1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, Bit 7) is set
2. The SECOND_TO_STS bit (TCO I/O Offset 06h, Bit 1) is not set (this indicates that
the system has not locked up).
3.20.4 Interrupts / SMI#
Intel® Xeon® Processor D-1500 Product Family SMBus controller uses PIRQB# as its
interrupt pin. However, the system can alternatively be set up to generate SMI#
instead of an interrupt, by setting the SMBUS_SMI_EN bit (D31:F0:Offset 40h:Bit 1).
Ta b l e 3- 4 2 and Tabl e 3- 4 3 specify how the various enable bits in the SMBus function
control the generation of the interrupt, Host and Slave SMI, and Wake internal signals.
The rows in the tables are additive, which means that if more than one row is true for a
particular scenario then the Results for all of the activated rows will occur.
Table 3-41. Enable for SMBALERT#
Event
INTREN (Host
Control I/O
Register, Offset
02h, Bit 0)
SMB_SMI_EN (Host
Configuration
Register,
D31:F3:Offset 40h,
Bit 1)
SMBALERT_DIS (Slave
Command I/O Register,
Offset 11h, Bit 2)
Result
SMBALERT# asserted
low (always reported
in Host Status
Register, Bit 5)
XX XWake generated
X1 0Slave SMI# generated
(SMBUS_SMI_STS)
10 0Interrupt generated